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S71GS256/128N based MCPs
Stacked Multi-Chip Product (MCP) 256/128 Megabit (16/8M x 16-bit) CMOS 3.0 Volt VCC and 1.8 V VIO MirrorBitTM Uniform Sector Page-mode Flash Memory with 64/32 Megabit (4/2M x 16-bit) 1.8V pSRAM
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
MCP Features Power supply voltage
-- Flash Memory VCC: 2.7V to 3.1V VIO: 1.65V to 1.95V -- pSRAM VCC: 1.7 V to 1.95 V
High Performance 110 ns access time 30 ns page read times Packages:
-- 8.0x11.6x1.2 mm FBGA (TLA084)
Operating Temperature
-- -25C to +85C (Wireless)
General Description
The S71GS Series is a product line of stacked Multi-chip Product (MCP) packages and consists of
One S29GL Flash memory die with 1.8 V VIO one 1.8 V pSRAM (Note)
Note: Burst mode features of the pSRAM in the S71GS family of MCPs is not available. This MCP uses the page mode operation which utilizes the page mode Flash and page mode feature-set of the pSRAM.
Publication Number S71GS256/128N_00
Revision A
Amendment 0
Issue Date December 17, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
Advance
Information
Product Selector Guide
Part Number Full Voltage Range VCC = 2.7 V to 3.1 V (Flash) VIO = 1.65 V to 1.95 V (Flash) VCC = 1.7 V to 1.95 V (pSRAM) S71GS256NC0
Speed/Voltage Option
Flash 110 110 30 30
pSRAM 70 70 25 25
Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (tpacc) Max. OE# Access Time (ns)
Part Number Full Voltage Range VCC = 2.7 V to 3.1 V (Flash) VIO = 1.65 V to 1.95 V (Flash) VCC = 1.7 V to 1.95 V (pSRAM)
S71GS128NB0
Speed/Voltage Option
Flash 110 110 30 30
pSRAM 70 70 25 25
Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (tpacc) Max. OE# Access Time (ns)
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S71GS256/128N based MCPs
S71GS256/128N_00_A0 December 17, 2004
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Information
S71GS256/128N based MCPs
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2 MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 15
Low VCC Write Inhibit ................................................................................61 Write Pulse "Glitch" Protection ................................................................ 61 Logical Inhibit .................................................................................................... 61 Power-Up Write Inhibit ................................................................................61
Common Flash Memory Interface (CFI) . . . . . . . 61
Table 8. CFI Query Identification String ................................ Table 9. System Interface String.......................................... Table 10. Device Geometry Definition ................................... Table 11. Primary Vendor-Specific Extended Query ................ 62 63 64 65
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 65
Reading Array Data ...........................................................................................66 Reset Command .................................................................................................66 Autoselect Command Sequence ................................................................... 66 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence ............................................................................ 67 Word Program Command Sequence .......................................................... 67 Unlock Bypass Command Sequence ........................................................68 Write Buffer Programming .........................................................................68 Accelerated Program ....................................................................................69
Figure 1. Write Buffer Programming Operation....................... 70 Figure 2. Program Operation ............................................... 71
S29GLxxxN MirrorBit
TM
Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 17 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 19 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
S29GL512N ....................................................................................................... 22 S29GL256N ...................................................................................................... 22 S29GL128N ...................................................................................................... 22
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23
Table 1. Device Bus Operations ........................................... 23
Program Suspend/Program Resume Command Sequence ..................... 71
Figure 3. Program Suspend/Program Resume ........................ 72
VersatileIOTM (VIO) Control .............................................................................23 Requirements for Reading Array Data .........................................................23 Page Mode Read ............................................................................................. 24 Writing Commands/Command Sequences ................................................ 24 Write Buffer .................................................................................................... 24 Accelerated Program Operation .............................................................. 24 Autoselect Functions .....................................................................................25 Standby Mode .......................................................................................................25 Automatic Sleep Mode ......................................................................................25 RESET#: Hardware Reset Pin .........................................................................25 Output Disable Mode ....................................................................................... 26
Table 2. Sector Address Table-S29GL512N ........................... 26 Table 3. Sector Address Table-S29GL256N ........................... 41 Table 4. Sector Address Table-S29GL128N ........................... 48
Chip Erase Command Sequence ................................................................... 72 Sector Erase Command Sequence .................................................................73
Figure 4. Erase Operation ................................................... 74
Erase Suspend/Erase Resume Commands .................................................. 74 Lock Register Command Set Definitions .................................................... 75 Password Protection Command Set Definitions ...................................... 75 Non-Volatile Sector Protection Command Set Definitions .................. 77 Global Volatile Sector Protection Freeze Command Set ...................... 77 Volatile Sector Protection Command Set .................................................. 78 Secured Silicon Sector Entry Command ..................................................... 79 Secured Silicon Sector Exit Command ........................................................ 79 Command Definitions ....................................................................................... 80
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16 .................................................................80
Autoselect Mode .................................................................................................52
Table 5. Autoselect Codes, (High Voltage Method) ................ 53
Write Operation Status ................................................................................... 83 DQ7: Data# Polling ........................................................................................... 83
Figure 5. Data# Polling Algorithm ........................................ 84
Sector Protection ................................................................................................53 Persistent Sector Protection .......................................................................53 Password Sector Protection ........................................................................53 WP# Hardware Protection .........................................................................53 Selecting a Sector Protection Mode .........................................................53 Advanced Sector Protection ...........................................................................54 Lock Register ........................................................................................................54
Table 6. Lock Register ........................................................ 55
RY/BY#: Ready/Busy# .......................................................................................84 DQ6: Toggle Bit I ............................................................................................... 85
Figure 6. Toggle Bit Algorithm ............................................. 86
DQ2: Toggle Bit II ..............................................................................................86 Reading Toggle Bits DQ6/DQ2 ..................................................................... 87 DQ5: Exceeded Timing Limits ........................................................................ 87 DQ3: Sector Erase Timer ................................................................................ 87 DQ1: Write-to-Buffer Abort ...........................................................................88
Table 13. Write Operation Status .........................................88
Persistent Sector Protection ...........................................................................55 Dynamic Protection Bit (DYB) ...................................................................55 Persistent Protection Bit (PPB) ..................................................................56 Persistent Protection Bit Lock (PPB Lock Bit) ......................................56
Table 7. Sector Protection Schemes ..................................... 57
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89
Figure 7. .......................................................................... 89 Figure 8. Maximum Positive Overshoot Waveform.......................................................... 89
Persistent Protection Mode Lock Bit ...........................................................57 Password Sector Protection ........................................................................... 58 Password and Password Protection Mode Lock Bit ............................... 58 64-bit Password ...................................................................................................59 Persistent Protection Bit Lock (PPB Lock Bit) ...........................................59 Secured Silicon Sector Flash Memory Region ............................................59 Write Protect (WP#) ........................................................................................ 61 Hardware Data Protection .............................................................................. 61
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 89 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 9. Test Setup........................................................... 91 Table 14. Test Specifications ...............................................91
Key to Switching Waveforms . . . . . . . . . . . . . . . . 91
Figure 10. Input Waveforms and Measurement Levels ............ 91
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 92 3
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Read-Only Operations-S29GL128N, S29GL256N, S29GL512N .......... 92
Figure 11. Read Operation Timings....................................... 93 Figure 12. Page Read Timings.............................................. 93
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength ............................................................................................................120
Table 20. Output Impedance ............................................. 120
Hardware Reset (RESET#) .............................................................................. 94
Figure 13. Reset Timings..................................................... 94
Erase and Program Operations-S29GL128N, S29GL256N, S29GL512N ...................................................................................95
Figure 14. Program Operation Timings .................................. 96 Figure 15. Accelerated Program Timing Diagram .................... 96 Figure 16. Chip/Sector Erase Operation Timings..................... 97 Figure 17. Data# Polling Timings (During Embedded Algorithms) ............................................ 98 Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99 Figure 19. DQ2 vs. DQ6 ...................................................... 99
WAIT Configuration (BCR[8]): Default = WAIT Transitions One Clock Before Data Valid/Invalid ...............................................................120 WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ...............120
Figure 33. WAIT Configuration (BCR[8] = 0) ....................... 120 Figure 34. WAIT Configuration (BCR[8] = 1) ....................... 121 Figure 35. WAIT Configuration During Burst Operation.......... 121
Latency Counter (BCR[13:11]): Default = Three-Clock Latency ......121
Table 21. Variable Latency Configuration Codes ................... 121 Figure 36. Latency Counter (Variable Initial Latency, No Refresh Collision) ........................................................................ 122
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N ........................................................100
Figure 20. Alternate CE# Controlled Write (Erase/ Program) Operation Timings.............................................. 101
Operating Mode (BCR[15]): Default = Asynchronous Operation .122 Refresh Configuration Register .....................................................................122
Table 22. Refresh Configuration Register Mapping ................ 123
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh .... 123
Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1) ....... 123 Table 24. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 124 Table 25. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 124
Erase And Programming Performance . . . . . . 102 TSOP Pin and BGA Package Capacitance . . . . 102
CellularRAM Type 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 General Description . . . . . . . . . . . . . . . . . . . . . . 103
Figure 21. Functional Block Diagram................................... 104 Table 15. Signal Descriptions .............................................105 Table 16. Bus Operations--Asynchronous Mode ....................106 Table 17. Bus Operations--Burst Mode ................................107
Deep Power-Down (RCR[4]): Default = DPD Disabled ..................124 Temperature Compensated Refresh (RCR[6:5]): Default = +85C Operation ..............................................................................................................124 Page Mode Operation (RCR[7]): Default = Disabled ........................124
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 125 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126
Table 26. Electrical Characteristics and Operating Conditions . 126 Table 27. Temperature Compensated Refresh Specifications and Conditions ....................................................................... 127 Table 28. Partial Array Refresh Specifications and Conditions . 127 Table 29. Deep Power-Down Specifications .......................... 127
Functional Description . . . . . . . . . . . . . . . . . . . . 107
Power-Up Initialization .................................................................................... 107
Figure 22. Power-Up Initialization Timing............................. 108
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 108
Asynchronous Mode ........................................................................................108
Figure 23. READ Operation (ADV# LOW)............................. 108 Figure 24. WRITE Operation (ADV# LOW) ........................... 109
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 37. AC Input/Output Reference Waveform................. 128 Figure 38. Output Load Circuit ........................................... 128 Table 30. Output Load Circuit ............................................ 128 Table 31. Asynchronous READ Cycle Timing Requirements .... 129 Table 32. Burst READ Cycle Timing Requirements ................ 130 Table 33. Asynchronous WRITE Cycle Timing Requirements ... 131 Table 34. Burst WRITE Cycle Timing Requirements ............... 131
Page Mode READ Operation ........................................................................109
Figure 25. Page Mode READ Operation (ADV# LOW)............. 110
Burst Mode Operation .....................................................................................110
Figure 26. Burst Mode READ (4-word burst) ........................ 111 Figure 27. Burst Mode WRITE (4-word burst)....................... 111
Timing Diagrams ................................................................................................ 132
Figure 39. Initialization Period ........................................... 132 Table 35. Initialization Timing Parameters ........................... 132 Figure 40. Asynchronous READ.......................................... 133 Table 36. Asynchronous READ Timing Parameters ................ 133 Figure 41. Asynchronous READ Using ADV# ........................ 135 Table 37. Asynchronous READ Timing Parameters Using ADV# 135 Figure 42. Page Mode READ .............................................. 137 Table 38. Asynchronous READ Timing Parameters--Page Mode Operation ....................................................................... 137 Figure 43. Single-Access Burst READ Operation--Variable Latency .......................................................................... 139 Table 39. Burst READ Timing Parameters--Single Access, Variable Latency .......................................................................... 139 Figure 44. Four-word Burst READ Operation--Variable Latency 141 Table 40. Burst READ Timing Parameters--4-word Burst ....... 142 Figure 45. Four-word Burst READ Operation (with LB#/UB#). 143 Table 41. Burst READ Timing Parameters--4-word Burst with LB#/ UB# ............................................................................... 144 Figure 46. READ Burst Suspend ......................................... 145 Table 42. Burst READ Timing Parameters--Burst Suspend ..... 145 Figure 47. Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition ................................. 146 Table 43. Burst READ Timing Parameters--BCR[8] = 0 ......... 146 Figure 48. CE#-Controlled Asynchronous WRITE .................. 147
Mixed-Mode Operation ................................................................................... 112 WAIT Operation ............................................................................................... 112
Figure 28. Wired or WAIT Configuration .............................. 112
LB#/UB# Operation .......................................................................................... 113
Figure 29. Refresh Collision During READ Operation.............. 113 Figure 30. Refresh Collision During WRITE Operation ............ 114
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 114
Standby Mode Operation ................................................................................ 114 Temperature Compensated Refresh ........................................................... 114 Partial Array Refresh ........................................................................................ 115 Deep Power-Down Operation ...................................................................... 115
Configuration Registers . . . . . . . . . . . . . . . . . . . . 115
Access Using CRE .............................................................................................. 115
Figure 31. Configuration Register WRITE, Asynchronous Mode Followed by READ ................................................................ 116 Figure 32. Configuration Register WRITE, Synchronous Mode Followed by READ0............................................................... 117
Bus Configuration Register ............................................................................. 117
Table 18. Bus Configuration Register Definition ....................118 Table 19. Sequence and Burst Length .................................119
Burst Length (BCR[2:0]): Default = Continuous Burst ...................... 119 Burst Wrap (BCR[3]): Default = No Wrap .......................................... 119
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Table 44. Asynchronous WRITE Timing Parameters--CE#-Controlled .............................................147 Figure 49. LB#/UB#-Controlled Asynchronous WRITE ........... 149 Table 45. Asynchronous WRITE Timing Parameters--LB#/UB#Controlled .......................................................................149 Figure 50. WE#-Controlled Asynchronous WRITE.................. 151 Table 46. Asynchronous WRITE Timing Parameters--WE#Controlled .......................................................................151 Figure 51. Asynchronous WRITE Using ADV#....................... 153 Table 47. Asynchronous WRITE Timing Parameters Using ADV# ....................................................154 Figure 52. Burst WRITE Operation ...................................... 155 Table 48. Burst WRITE Timing Parameters ...........................156 Figure 53. Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition ................................. 157 Table 49. Burst WRITE Timing Parameters--BCR[8] = 0 ........157 Figure 54. Burst WRITE Followed by Burst READ .................. 158 Table 50. WRITE Timing Parameters--Burst WRITE Followed by Burst READ .....................................................................158 Table 51. READ Timing Parameters--Burst WRITE Followed by Burst READ ..............................................................................158 Figure 55. Asynchronous WRITE Followed by Burst READ ...... 159 Table 52. WRITE Timing Parameters--Asynchronous WRITE Followed by Burst READ ....................................................160 Table 53. READ Timing Parameters--Asynchronous WRITE Followed by Burst READ .................................................................160 Figure 56. Asynchronous WRITE (ADV# LOW) Followed By Burst READ.............................................................................. 161 Table 54. Asynchronous WRITE Timing Parameters--ADV# LOW ...................................................161 Table 55. Burst READ Timing Parameters ............................162 Figure 57. Burst READ Followed by Asynchronous WRITE (WE#-Controlled) ........................................................................... 163 Table 56. Burst READ Timing Parameters ............................164 Table 57. Asynchronous WRITE Timing Parameters--WE# Controlled .............................................164 Figure 58. Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................. 165 Table 58. Burst READ Timing Parameters ............................166 Table 59. Asynchronous WRITE Timing Parameters Using ADV# ....................................................166 Figure 59. Asynchronous WRITE Followed by Asynchronous READ-- ADV# LOW...................................................................... 167 Table 60. WRITE Timing Parameters--ADV# LOW .................167 Table 61. READ Timing Parameters--ADV# LOW ..................168 Figure 60. Asynchronous WRITE Followed by Asynchronous READ ......................................................... 169 Table 62. WRITE Timing Parameters--Asynchronous WRITE Followed by Asynchronous READ ........................................169 Table 63. READ Timing Parameters--Asynchronous WRITE Followed by Asynchronous READ .....................................................170
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 General Description . . . . . . . . . . . . . . . . . . . . . . 173
Figure 64. Functional Block Diagram................................... 174 Table 65. Pin Descriptions ................................................. 174 Table 66. Bus Operations--Asynchronous Mode ................... 175
Functional Description . . . . . . . . . . . . . . . . . . . . .176
Power-Up Initialization ....................................................................................176
Figure 65. Power-Up Initialization Timing ............................ 176
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 176
Asynchronous Mode ........................................................................................176
Figure 66. READ Operation................................................ 177 Figure 67. WRITE Operation .............................................. 177
Page Mode READ Operation ........................................................................ 177
Figure 68. Page Mode READ Operation................................ 178
LB# / UB# Operation ......................................................................................178
Low Power Operation . . . . . . . . . . . . . . . . . . . . . 178
Standby Mode Operation ...............................................................................178 Temperature Compensated Refresh ...........................................................178 Partial Array Refresh ........................................................................................179 Deep Power-Down Operation .....................................................................179 Configuration Register Operation ...............................................................179
Figure 69. Load Configuration Register Operation................. 180 Table 67. Configuration Register Bit Mapping ....................... 181 Table 68. 64Mb Address Patterns for PAR (CR[4] = 1) .......... 181
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 182 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 183
Table 69. Electrical Characteristics and Operating Conditions . 183 Table 70. Temperature Compensated Refresh Specifications and Conditions ....................................................................... 183 Table 71. Partial Array Refresh Specifications and Conditions . 184 Table 72. Deep Power-Down Specifications .......................... 184 Table 73. Capacitance Specifications and Conditions ............. 184
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 70. AC Input/Output Reference Waveform................. 184 Figure 71. Output Load Circuit ........................................... 184 Table 74. Output Load Circuit ............................................ 184 Table 75. READ Cycle Timing Requirements ......................... 185 Table 76. WRITE Cycle Timing Requirements ....................... 186 Table 77. Load Configuration Register Timing Requirements .. 186 Table 78. Deep Power Down Timing Requirements ............... 186 Table 79. Power-up Initialization Timing Parameters ............. 187 Figure 72. Power-up Initialization Period ............................. 187 Figure 73. Load Configuration Register Timing ..................... 187 Table 80. Load Configuration Register Timing Requirements .. 187 Figure 74. Deep Power Down Entry/Exit TIming ................... 188 Table 81. Load Configuration Register Timing Requirements .. 188 Figure 75. Single READ Operation (WE# = VIH) ................... 188 Table 82. READ Timing Parameters .................................... 189 Figure 76. Page Mode Read Operation (WE# = VIH) ............. 189 Table 83. Page Mode READ Timing Parameters .................... 189 Figure 77. WRITE Cycle (WE# Control) ............................... 190 Table 84. Write Timing Parameters ..................................... 190 Figure 78. Write Timing Parameters (CE# Control) ............... 191 Table 85. Write Timing Parameters (CE# Control) ................ 191 Figure 79. WRITE Cycle (LB# / UB# Control)....................... 192 Table 86. Write Timing Parameters (LB# / UB# Control) ....... 192
How Extended Timings Impact CellularRAMTM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Introduction ........................................................................................................ 170 Asynchronous WRITE Operation ................................................................ 171
Figure 61. Extended Timing for tCEM.............................................. 171 Figure 62. Extended Timing for tTM................................................ 171 Table 64. Extended Cycle Impact on READ and WRITE Cycles 171
Extended WRITE Timing-- Asynchronous WRITE Operation ...... 171
Figure 63. Extended WRITE Operation ................................ 172
Page Mode READ Operation ........................................................................ 172 Burst-Mode Operation .................................................................................... 172 Summary .............................................................................................................. 172
How Extended Timings Impact CellularRAMTM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Introduction ........................................................................................................193 Operation When Page Mode is Disabled .................................................. 193 Operation When Page Mode is Enabled ....................................................193
Figure 80. Extended Timing for tCEM.............................................. Figure 81. Extended Timing for tTM................................................
193 193
CellularRAM-2A
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Impact on Extended WRITE Operations ..................................................194
Figure 82. Extended Timing for tCEM (2) .............................. 194 Figure 83. Extended WRITE Operation ................................ 194
Revision Summary
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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MCP Block Diagrams
(256 Mb Flash + 64 Mb pSRAM)
F-VIO F-VCC Flash-only Address Shared Address WP#/ACC F1-CE# OE# WE# F-RST# 2 22 F-VCC VIO DQ15 to DQ0
16
DQ15 to DQ0
WP#/ACC CE# OE# WE# F-RST# Flash
RY/BY#
RY/BY# VSS
R- VCC 22 R-VCC R-VIO I/O15 to I/O0 WE# OE# pSRAM UB# LB# VSSQ ZZ# R-CE1# 16
R-UB# R-LB# ZZ# R-CE1#
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(128 Mb Flash + 32 Mb pSRAM)
F-VIO F-VCC Flash-only Address Shared Address WP#/ACC F1-CE# OE# WE# F-RST# 2 21 F-VCC VIO DQ15 to DQ0
16
DQ15 to DQ0
WP#/ACC CE# OE# WE# F-RST# Flash
RY/BY#
RY/BY# VSS
R-VCC 21 R-VCC R-VIO I/O15 to I/O0 WE# OE# pSRAM UB# LB# VSSQ CRE R-CE1# 16
R-UB# R-LB# CRE R-CE1#
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Connection Diagrams
256 Mb Flash + 64 Mb pSRAM Pinout
84-ball Fine-Pitch Ball Grid Array 256 Mb Flash + 64 Mb pSRAM Pinout (Top View, Balls Facing Down)
Legend
A1 DNU B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 F1-CE# J2 R-CE1# K2 RFU L2 RFU M1 DNU B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 RFU C4 B5 RFU C5 B6 RFU C6 B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 R-VIO B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 F-VIO B9 RFU C9 RFU D9
A10 DNU Shared
Flash only
R-LB# WP#/ACC WE# D4 D5 D6 RFU E6 A20 F6 A23 G6 RFU H6 DQ4 J6 R-VCC K6 RFU L6 RFU
RAM only A15 E9 A21 F9 A22 G9 A16 H9 ZZ# J9 VSS K9 RFU L9 RFU M10 DNU Reserved for Future Use
R-UB# F-RST# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU E5 RY/BY# F5 RFU G5 RFU H5 DQ3 J5 F-VCC K5 DQ11 L5 F-VCC
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128 Mb Flash + 32 Mb pSRAM Pinout
84-ball Fine-Pitch Ball Grid Array 128 Mb Flash + 32 Mb pSRAM Pinout (Top View, Balls Facing Down)
Legend
A1 DNU B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 F1-CE# J2 R-CE1# K2 RFU L2 RFU M1 DNU B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 RFU C4 B5 RFU C5 B6 RFU C6 B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 R-VIO B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 F-VIO B9 RFU C9 RFU D9
A10 DNU Shared
Flash only
R-LB# WP#/ACC WE# D4 D5 D6 RFU E6 A20 F6 RFU G6 RFU H6 DQ4 J6 R-VCC K6 RFU L6 RFU
RAM only A15 E9 A21 F9 A22 G9 A16 H9 CRE J9 VSS K9 RFU L9 RFU M10 DNU Reserved for Future Use
R-UB# F-RST# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU E5 RY/BY# F5 RFU G5 RFU H5 DQ3 J5 F-VCC K5 DQ11 L5 F-VCC
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Input/Output Descriptions
A23-A0 A22-A0 DQ15-DQ0 OE# WE# VSS NC F-RST# WP#/ACC R-CE1# ZZ# CRE = = = = = = = = = = = = 24 Address inputs (256 Mb) 23 Address inputs (128 Mb) Data input/output Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Ground No Connect; not connected internally Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input / programming acceleration input. Chip-enable input for pSRAM. pSRAM Sleep mode Configuration Register Enable. CRE is used only for power savings, but does not enable burst operations. Chip-enable input for Flash 1. Flash 3.0 Volt-only single power supply. pSRAM Power Supply. Upper Byte Control (pSRAM). Lower Byte Control (pSRAM). Reserved for future use. Ready/Busy output. Flash Input/Output Buffer Power Supply pSRAM Input/Output Buffer Power Supply
F1-CE# F-VCC R-VCC R-UB# R-LB# RFU RY/BY# F-VIO R-VIO
= = = = = = = = =
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Logic Symbol
Max (Note 1) AMax (Note 2) -A0 R-CE1# DQ15-DQ0 16
OE# WE# WP#/ACC WE# F-RST# UB# F1-CE# CRE (Note 3) ZZ# (Note 4) RY/BY#
Notes: 1. Max = 24 [256 Mb Flash], 23 [128 Mb Flash]. 2. AMax = A23 [256 Mb Flash], A22 [128 Mb Flash]. 3. CRE is available only in Synchronous pSRAM. 4. ZZ# is available only in Asynchronous pSRAM.
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S71GS256/128N_00_A0 December 17, 2004
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Ordering Information
The order number (Valid Combination) is formed by the following:
S71GS
256
N
C0
BA
W
AK
0
PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel PACKAGE MODIFIER / MODEL NUMBER See Valid Combinations table TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE BA = Very Thin Fine-pitch BGA Lead (Pb)-free compliant package BF = Very Thin Fine-pitch BGA Lead (Pb)-free package pSRAM DENSITY C0 = 64 Mb pSRAM B0 = 32 Mb pSRAM PROCESS TECHNOLOGY N = 110 nm, MirrorBitTM Technology FLASH DENSITY 256 = 256 Mb 128 = 128 Mb PRODUCT FAMILY S71GS Multi-chip Product (MCP) 3.0 Volt-only VCC and 1.8 V VIOUniform Sector Page Mode Flash Memory with 1.8 Volt pSRAM
S71GS256NC0 Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number AK S71GS256NC0 BAW AP AK AP 0, 2, 3 (Note 1) Flash Initial/Page Speed (ns) Address Sector Protection Lowest Add Highest Add Lowest Add Highest Add CellRam 2A (Note 3) (p)SRAM Type/ Access Time (ns)
Packing Type
(p)SRAM Supplier
Package Type 8mmx11.6mm 84-ball Lead (Pb)-free Compliant 8mmx11.6mm 84-ball Lead (Pb)-free
Package Marking
110/30
70 / 25
(Note 2)
S71GS256NC0
BFW
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 3. For specifications, refer to the CellularRam 2A module.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
December 17, 2004 S71GS256/128N_00_A0
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S71GS128NB0 Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number AK S71GS128NB0 BAW AP AK AP 0, 2, 3 (Note 1) Flash Initial/Page Speed (ns) Address Sector Protection Lowest Add Highest Add Lowest Add Highest Add CellRam 2 (Note 3) (p)SRAM Type/ Access Time (ns)
Packing Type
(p)SRAM Supplier
Package Type 8mmx11.6mm 84-ball Lead (Pb)-free Compliant 8mmx11.6mm 84-ball Lead (Pb)-free
Package Marking
110/30
70 / 25
(Note 2)
S71GS128NB0
BFW
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. 3. For specifications, refer to the CellularRam 2 module.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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S71GS256/128N_00_A0 December 17, 2004
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Physical Dimensions
TLA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm MCP Compatible Package
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 TLA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10, E1,E10,F1,F10,G1,G10, H1,H10,J1,J10,K1,K10,L1,L10, M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
December 17, 2004 S71GS256/128N_00_A0
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S29GLxxxN MirrorBitTM Flash Family
S29GL512N, S29GL256N, S29GL128N 512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit process technology
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
Architectural Advantages
Single power supply operation -- 3 volt read, erase, and program operations Enhanced VersatileI/OTM control -- All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC Manufactured on 110 nm MirrorBit process technology Secured Silicon Sector region -- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- S29GL512N: Five hundred twelve 64 Kword (128 Kbyte) sectors -- S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors -- S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection 100,000 erase cycles per sector typical 20-year data retention typical -- 90 ns access time (S29GL128N, S29GL256N, S29GL512N) -- 8-word/16-byte page read buffer -- 25 ns page read times -- 16-word/32-byte write buffer reduces overall programming time for multiple-word updates Low power consumption (typical values at 3.0 V, 5 MHz) -- 25 mA typical active read current; -- 50 mA typical erase/program current -- 1 A typical standby mode current
Software & Hardware Features
Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Advanced Sector Protection -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion
Performance Characteristics
High performance
Publication Number S29GLxxxN_MCP
Revision A
Amendment 1
Issue Date December 15, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
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Information
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the "Product Selector Guide" section. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The Enhanced VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on all input levels (address, chip control, and DQ input levels) to the same voltage level that is asserted on the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as required. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be
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tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
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Product Selector Guide
S29GL512N
Part Number VCC = 2.7-3.6 V VCC = 3.0-3.6V Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = 3.0-3.6V 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL512N 10 11 11
Speed Option
S29GL256N
Part Number VCC = 2.7-3.6 V VCC = Regulated (3.0-3.6V) Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = Regulated (3.0-3.6V) 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL256N 10 11 11
Speed Option
S29GL128N
Part Number VCC = 2.7-3.6 V VCC = Regulated (3.0-3.6V) Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = Regulated (3.0-3.6V) 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL128N 10 11 11
Speed Option
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Block Diagram
RY/BY#
VCC VSS VIO RESET# WE# WP#/ACC Sector Switches Erase Voltage Generator Input/Output Buffers
DQ15-DQ0 (A-1)
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Address Latch
Y-Decoder
Y-Gating
Timer
X-Decoder
Cell Matrix
AMax**-A0
Notes: 1. AMax GL512N = A24, AMax GL256N = A23, AMax GL128N = A22
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S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
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Pin Description
A24-A0 A23-A0 A22-A0 DQ14-DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# RY/BY# VCC VIO VSS NC = = = = = = = = = = = = 25 Address inputs (512 Mb) 24 Address inputs (256 Mb) 23 Address inputs (128 Mb) 15 Data inputs/outputs DQ15 (Data input/output, word mode), A-1 (LSB Address input Chip Enable input Output Enable input Write Enable input Hardware Write Protect input; Acceleration input Hardware Reset Pin input Ready/Busy output 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Output Buffer power Device Ground Pin Not Connected Internally
= = =
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Logic Symbol
S29GL512N
25 A24-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
S29GL256N
24 A23-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
S29GL128N
23 A22-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
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S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
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Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset VCC CE# L L L OE# L H H X H X
Device Bus Operations
WE# H L L X H X RESET# H H H VCC 0.3 V H L WP#/ ACC X Note 2 VHH H X X Addresses (Note 1) AIN AIN AIN X X X DQ0-DQ15 DOUT (Note 3) (Note 3) High-Z High-Z High-Z
0.3 V
L X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 11.5-12.5V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are AMax:A0 in word mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Write Protect (WP#)". All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and Figure 5).
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See Ordering Information for VIO options on this device. For example, a VI/O of 1.65 V to 3.6 V allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8-V or 3-V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory
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content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" on page 66 for more information. Refer to the AC ReadOnly Operations table for timing specifications and to Figure 11 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3. Address bits A2-A0 determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2, Table 4, and Table 5 indicate the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.
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If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" section on page 52 and "Autoselect Command Sequence" section on page 66 sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the "DC Characteristics" section on page 90 for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the "DC Characteristics" section on page 90 for the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
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Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2.
Sector Address Table-S29GL512N
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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S29GLxxxN MirrorBitTM Flash Family
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF
Sector SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF
Sector SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 0800000-080FFFF
Sector SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
A24-A16 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0810000-081FFFF 0820000-082FFFF 0830000-083FFFF 0840000-084FFFF 0850000-085FFFF 0860000-086FFFF 0870000-087FFFF 0880000-088FFFF 0890000-089FFFF 08A0000-08AFFFF 08B0000-08BFFFF 08C0000-08CFFFF 08D0000-08DFFFF 08E0000-08EFFFF 08F0000-08FFFFF 0900000-090FFFF 0910000-091FFFF 0920000-092FFFF 0930000-093FFFF 0940000-094FFFF 0950000-095FFFF 0960000-096FFFF 0970000-097FFFF 0980000-098FFFF 0990000-099FFFF 09A0000-09AFFFF 09B0000-09BFFFF 09C0000-09CFFFF 09D0000-09DFFFF 09E0000-09EFFFF 09F0000-09FFFFF 0A00000-0A0FFFF 0A10000-0A1FFFF 0A20000-0A2FFFF 0A30000-0A3FFFF
Sector SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0A40000-0A4FFFF 0A50000-0A5FFFF 0A60000-0A6FFFF 0A70000-0A7FFFF 0A80000-0A8FFFF 0A90000-0A9FFFF 0AA0000-0AAFFFF 0AB0000-0ABFFFF 0AC0000-0ACFFFF 0AD0000-0ADFFFF 0AE0000-0AEFFFF 0AF0000-0AFFFFF 0B00000-0B0FFFF 0B10000-0B1FFFF 0B20000-0B2FFFF 0B30000-0B3FFFF 0B40000-0B4FFFF 0B50000-0B5FFFF 0B60000-0B6FFFF 0B70000-0B7FFFF 0B80000-0B8FFFF 0B90000-0B9FFFF 0BA0000-0BAFFFF 0BB0000-0BBFFFF 0BC0000-0BCFFFF 0BD0000-0BDFFFF 0BE0000-0BEFFFF 0BF0000-0BFFFFF 0C00000-0C0FFFF 0C10000-0C1FFFF 0C20000-0C2FFFF 0C30000-0C3FFFF 0C40000-0C4FFFF 0C50000-0C5FFFF 0C60000-0C6FFFF
Sector SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0C70000-0C7FFFF 0C80000-0C8FFFF 0C90000-0C9FFFF 0CA0000-0CAFFFF 0CB0000-0CBFFFF 0CC0000-0CCFFFF 0CD0000-0CDFFFF 0CE0000-0CEFFFF 0CF0000-0CFFFFF 0D00000-0D0FFFF 0D10000-0D1FFFF 0D20000-0D2FFFF 0D30000-0D3FFFF 0D40000-0D4FFFF 0D50000-0D5FFFF 0D60000-0D6FFFF 0D70000-0D7FFFF 0D80000-0D8FFFF 0D90000-0D9FFFF 0DA0000-0DAFFFF 0DB0000-0DBFFFF 0DC0000-0DCFFFF 0DD0000-0DDFFFF 0DE0000-0DEFFFF 0DF0000-0DFFFFF 0E00000-0E0FFFF 0E10000-0E1FFFF 0E20000-0E2FFFF 0E30000-0E3FFFF 0E40000-0E4FFFF 0E50000-0E5FFFF 0E60000-0E6FFFF 0E70000-0E7FFFF 0E80000-0E8FFFF 0E90000-0E9FFFF
Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
A24-A16 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0EA0000-0EAFFFF 0EB0000-0EBFFFF 0EC0000-0ECFFFF 0ED0000-0EDFFFF 0EE0000-0EEFFFF 0EF0000-0EFFFFF 0F00000-0F0FFFF 0F10000-0F1FFFF 0F20000-0F2FFFF 0F30000-0F3FFFF 0F40000-0F4FFFF 0F50000-0F5FFFF 0F60000-0F6FFFF 0F70000-0F7FFFF 0F80000-0F8FFFF 0F90000-0F9FFFF 0FA0000-0FAFFFF 0FB0000-0FBFFFF 0FC0000-0FCFFFF 0FD0000-0FDFFFF 0FE0000-0FEFFFF 0FF0000-0FFFFFF 1000000-100FFFF 1010000-101FFFF 1020000-102FFFF 1030000-103FFFF 1040000-104FFFF 1050000-105FFFF 1060000-106FFFF 1070000-107FFFF 1080000-108FFFF 1090000-109FFFF 10A0000-10AFFFF 10B0000-10BFFFF 10C0000-10CFFFF
Sector SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 10D0000-10DFFFF 10E0000-10EFFFF 10F0000-10FFFFF 1100000-110FFFF 1110000-111FFFF 1120000-112FFFF 1130000-113FFFF 1140000-114FFFF 1150000-115FFFF 1160000-116FFFF 1170000-117FFFF 1180000-118FFFF 1190000-119FFFF 11A0000-11AFFFF 11B0000-11BFFFF 11C0000-11CFFFF 11D0000-11DFFFF 11E0000-11EFFFF 11F0000-11FFFFF 1200000-120FFFF 1210000-121FFFF 1220000-122FFFF 1230000-123FFFF 1240000-124FFFF 1250000-125FFFF 1260000-126FFFF 1270000-127FFFF 1280000-128FFFF 1290000-129FFFF 12A0000-12AFFFF 12B0000-12BFFFF 12C0000-12CFFFF 12D0000-12DFFFF 12E0000-12EFFFF 12F0000-12FFFFF
Sector SA269 SA270 SA271 SA272 SA273 SA274 SA275 SA276 SA277 SA278 SA279 SA280 SA281 SA282 SA283 SA284 SA285 SA286 SA287 SA288 SA289 SA290 SA291 SA292 SA293 SA294 SA295 SA296 SA297 SA298 SA299 SA300 SA301 SA302 SA303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1300000-130FFFF 1310000-131FFFF 1320000-132FFFF 1330000-133FFFF 1340000-134FFFF 1350000-135FFFF 1360000-136FFFF 1370000-137FFFF 1380000-138FFFF 1390000-139FFFF 13A0000-13AFFFF 13B0000-13BFFFF 13C0000-13CFFFF 13D0000-13DFFFF 13E0000-13EFFFF 13F0000-13FFFFF 1400000-140FFFF 1410000-141FFFF 1420000-142FFFF 1430000-143FFFF 1440000-144FFFF 1450000-145FFFF 1460000-146FFFF 1470000-147FFFF 1480000-148FFFF 1490000-149FFFF 14A0000-14AFFFF 14B0000-14BFFFF 14C0000-14CFFFF 14D0000-14DFFFF 14E0000-14EFFFF 14F0000-14FFFFF 1500000-150FFFF 1510000-151FFFF 1520000-152FFFF
Sector SA304 SA305 SA306 SA307 SA308 SA309 SA310 SA311 SA312 SA313 SA314 SA315 SA316 SA317 SA318 SA319 SA320 SA321 SA322 SA323 SA324 SA325 SA326 SA327 SA328 SA329 SA330 SA331 SA332 SA333 SA334 SA335 SA336 SA337 SA338 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1530000-153FFFF 1540000-154FFFF 1550000-155FFFF 1560000-156FFFF 1570000-157FFFF 1580000-158FFFF 1590000-159FFFF 15A0000-15AFFFF 15B0000-15BFFFF 15C0000-15CFFFF 15D0000-15DFFFF 15E0000-15EFFFF 15F0000-15FFFFF 1600000-160FFFF 1610000-161FFFF 1620000-162FFFF 1630000-163FFFF 1640000-164FFFF 1650000-165FFFF 1660000-166FFFF 1670000-167FFFF 1680000-168FFFF 1690000-169FFFF 16A0000-16AFFFF 16B0000-16BFFFF 16C0000-16CFFFF 16D0000-16DFFFF 16E0000-16EFFFF 16F0000-16FFFFF 1700000-170FFFF 1710000-171FFFF 1720000-172FFFF 1730000-173FFFF 1740000-174FFFF 1750000-175FFFF
Sector SA339 SA340 SA341 SA342 SA343 SA344 SA345 SA346 SA347 SA348 SA349 SA350 SA351 SA352 SA353 SA354 SA355 SA356 SA357 SA358 SA359 SA360 SA361 SA362 SA363 SA364 SA365 SA366 SA367 SA368 SA369 SA370 SA371 SA372 SA373 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
36
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1760000-176FFFF 1770000-177FFFF 1780000-178FFFF 1790000-179FFFF 17A0000-17AFFFF 17B0000-17BFFFF 17C0000-17CFFFF 17D0000-17DFFFF 17E0000-17EFFFF 17F0000-17FFFFF 1800000-180FFFF 1810000-181FFFF 1820000-182FFFF 1830000-183FFFF 1840000-184FFFF 1850000-185FFFF 1860000-186FFFF 1870000-187FFFF 1880000-188FFFF 1890000-189FFFF 18A0000-18AFFFF 18B0000-18BFFFF 18C0000-18CFFFF 18D0000-18DFFFF 18E0000-18EFFFF 18F0000-18FFFFF 1900000-190FFFF 1910000-191FFFF 1920000-192FFFF 1930000-193FFFF 1940000-194FFFF 1950000-195FFFF 1960000-196FFFF 1970000-197FFFF 1980000-198FFFF
Sector SA374 SA375 SA376 SA377 SA378 SA379 SA380 SA381 SA382 SA383 SA384 SA385 SA386 SA387 SA388 SA389 SA390 SA391 SA392 SA393 SA394 SA395 SA396 SA397 SA398 SA399 SA400 SA401 SA402 SA403 SA404 SA405 SA406 SA407 SA408 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1990000-199FFFF 19A0000-19AFFFF 19B0000-19BFFFF 19C0000-19CFFFF 19D0000-19DFFFF 19E0000-19EFFFF 19F0000-19FFFFF 1A00000-1A0FFFF 1A10000-1A1FFFF 1A20000-1A2FFFF 1A30000-1A3FFFF 1A40000-1A4FFFF 1A50000-1A5FFFF 1A60000-1A6FFFF 1A70000-1A7FFFF 1A80000-1A8FFFF 1A90000-1A9FFFF 1AA0000-1AAFFFF 1AB0000-1ABFFFF 1AC0000-1ACFFFF 1AD0000-1ADFFFF 1AE0000-1AEFFFF 1AF0000-1AFFFFF 1B00000-1B0FFFF 1B10000-1B1FFFF 1B20000-1B2FFFF 1B30000-1B3FFFF 1B40000-1B4FFFF 1B50000-1B5FFFF 1B60000-1B6FFFF 1B70000-1B7FFFF 1B80000-1B8FFFF 1B90000-1B9FFFF 1BA0000-1BAFFFF 1BB0000-1BBFFFF
Sector SA409 SA410 SA411 SA412 SA413 SA414 SA415 SA416 SA417 SA418 SA419 SA420 SA421 SA422 SA423 SA424 SA425 SA426 SA427 SA428 SA429 SA430 SA431 SA432 SA433 SA434 SA435 SA436 SA437 SA438 SA439 SA440 SA441 SA442 SA443 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
38
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1BC0000-1BCFFFF 1BD0000-1BDFFFF 1BE0000-1BEFFFF 1BF0000-1BFFFFF 1C00000-1C0FFFF 1C10000-1C1FFFF 1C20000-1C2FFFF 1C30000-1C3FFFF 1C40000-1C4FFFF 1C50000-1C5FFFF 1C60000-1C6FFFF 1C70000-1C7FFFF 1C80000-1C8FFFF 1C90000-1C9FFFF 1CA0000-1CAFFFF 1CB0000-1CBFFFF 1CC0000-1CCFFFF 1CD0000-1CDFFFF 1CE0000-1CEFFFF 1CF0000-1CFFFFF 1D00000-1D0FFFF 1D10000-1D1FFFF 1D20000-1D2FFFF 1D30000-1D3FFFF 1D40000-1D4FFFF 1D50000-1D5FFFF 1D60000-1D6FFFF 1D70000-1D7FFFF 1D80000-1D8FFFF 1D90000-1D9FFFF 1DA0000-1DAFFFF 1DB0000-1DBFFFF 1DC0000-1DCFFFF 1DD0000-1DDFFFF 1DE0000-1DEFFFF
Sector SA444 SA445 SA446 SA447 SA448 SA449 SA450 SA451 SA452 SA453 SA454 SA455 SA456 SA457 SA458 SA459 SA460 SA461 SA462 SA463 SA464 SA465 SA466 SA467 SA468 SA469 SA470 SA471 SA472 SA473 SA474 SA475 SA476 SA477 SA478 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1DF0000-1DFFFFF 1E00000-1E0FFFF 1E10000-1E1FFFF 1E20000-1E2FFFF 1E30000-1E3FFFF 1E40000-1E4FFFF 1E50000-1E5FFFF 1E60000-1E6FFFF 1E70000-1E7FFFF 1E80000-1E8FFFF 1E90000-1E9FFFF 1EA0000-1EAFFFF 1EB0000-1EBFFFF 1EC0000-1ECFFFF 1ED0000-1EDFFFF 1EE0000-1EEFFFF 1EF0000-1EFFFFF 1F00000-1F0FFFF 1F10000-1F1FFFF 1F20000-1F2FFFF 1F30000-1F3FFFF 1F40000-1F4FFFF 1F50000-1F5FFFF 1F60000-1F6FFFF 1F70000-1F7FFFF 1F80000-1F8FFFF 1F90000-1F9FFFF 1FA0000-1FAFFFF 1FB0000-1FBFFFF 1FC0000-1FCFFFF 1FD0000-1FDFFFF 1FE0000-1FEFFFF 1FF0000-1FFFFFF
Sector SA479 SA480 SA481 SA482 SA483 SA484 SA485 SA486 SA487 SA488 SA489 SA490 SA491 SA492 SA493 SA494 SA495 SA496 SA497 SA498 SA499 SA500 SA501 SA502 SA503 SA504 SA505 SA506 SA507 SA508 SA509 SA510 SA511 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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S29GLxxxN MirrorBitTM Flash Family
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Information
Table 3.
Sector Address Table-S29GL256N
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
A23-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
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Information
Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF
Sector SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
A23-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0
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Information
Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF
Sector SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A23-A16 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
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Information
Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 0800000-080FFFF 0810000-081FFFF 0820000-082FFFF 0830000-083FFFF 0840000-084FFFF 0850000-085FFFF 0860000-086FFFF 0870000-087FFFF 0880000-088FFFF 0890000-089FFFF 08A0000-08AFFFF
Sector SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
A23-A16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1
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Information
Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 08B0000-08BFFFF 08C0000-08CFFFF 08D0000-08DFFFF 08E0000-08EFFFF 08F0000-08FFFFF 0900000-090FFFF 0910000-091FFFF 0920000-092FFFF 0930000-093FFFF 0940000-094FFFF 0950000-095FFFF 0960000-096FFFF 0970000-097FFFF 0980000-098FFFF 0990000-099FFFF 09A0000-09AFFFF 09B0000-09BFFFF 09C0000-09CFFFF 09D0000-09DFFFF 09E0000-09EFFFF 09F0000-09FFFFF 0A00000-0A0FFFF 0A10000-0A1FFFF 0A20000-0A2FFFF 0A30000-0A3FFFF 0A40000-0A4FFFF 0A50000-0A5FFFF 0A60000-0A6FFFF 0A70000-0A7FFFF 0A80000-0A8FFFF 0A90000-0A9FFFF 0AA0000-0AAFFFF 0AB0000-0ABFFFF 0AC0000-0ACFFFF 0AD0000-0ADFFFF
Sector SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1
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Information
Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0AE0000-0AEFFFF 0AF0000-0AFFFFF 0B00000-0B0FFFF 0B10000-0B1FFFF 0B20000-0B2FFFF 0B30000-0B3FFFF 0B40000-0B4FFFF 0B50000-0B5FFFF 0B60000-0B6FFFF 0B70000-0B7FFFF 0B80000-0B8FFFF 0B90000-0B9FFFF 0BA0000-0BAFFFF 0BB0000-0BBFFFF 0BC0000-0BCFFFF 0BD0000-0BDFFFF 0BE0000-0BEFFFF 0BF0000-0BFFFFF 0C00000-0C0FFFF 0C10000-0C1FFFF 0C20000-0C2FFFF 0C30000-0C3FFFF 0C40000-0C4FFFF 0C50000-0C5FFFF 0C60000-0C6FFFF 0C70000-0C7FFFF 0C80000-0C8FFFF 0C90000-0C9FFFF 0CA0000-0CAFFFF 0CB0000-0CBFFFF 0CC0000-0CCFFFF 0CD0000-0CDFFFF 0CE0000-0CEFFFF 0CF0000-0CFFFFF 0D00000-0D0FFFF
Sector SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
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S29GLxxxN_MCP_A1 December 15, 2004
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Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0D10000-0D1FFFF 0D20000-0D2FFFF 0D30000-0D3FFFF 0D40000-0D4FFFF 0D50000-0D5FFFF 0D60000-0D6FFFF 0D70000-0D7FFFF 0D80000-0D8FFFF 0D90000-0D9FFFF 0DA0000-0DAFFFF 0DB0000-0DBFFFF 0DC0000-0DCFFFF 0DD0000-0DDFFFF 0DE0000-0DEFFFF 0DF0000-0DFFFFF 0E00000-0E0FFFF 0E10000-0E1FFFF 0E20000-0E2FFFF 0E30000-0E3FFFF 0E40000-0E4FFFF 0E50000-0E5FFFF 0E60000-0E6FFFF 0E70000-0E7FFFF 0E80000-0E8FFFF 0E90000-0E9FFFF 0EA0000-0EAFFFF 0EB0000-0EBFFFF 0EC0000-0ECFFFF 0ED0000-0EDFFFF 0EE0000-0EEFFFF 0EF0000-0EFFFFF 0F00000-0F0FFFF 0F10000-0F1FFFF 0F20000-0F2FFFF 0F30000-0F3FFFF
Sector SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
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Table 3.
Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0F40000-0F4FFFF 0F50000-0F5FFFF 0F60000-0F6FFFF 0F70000-0F7FFFF 0F80000-0F8FFFF 0F90000-0F9FFFF 0FA0000-0FAFFFF 0FB0000-0FBFFFF 0FC0000-0FCFFFF 0FD0000-0FDFFFF 0FE0000-0FEFFFF 0FF0000-0FFFFFF
Sector SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1
Table 4.
Sector Address Table-S29GL128N
Sector Size (Kbytes/ Kwords) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
A22-A16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF
Sector SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
A22-A16 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF
Sector SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A22-A16 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF
Sector SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A22-A16 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 1 0 0 1 1 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF
Sector SA123 SA124 SA125 SA126 SA127 1 1 1 1 1 1 1 1 1 1
A22-A16 1 1 1 1 1 0 1 1 1 1
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 5 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.
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Table 5.
Description Manufacturer ID: Spansion Product Device ID Device ID Device ID S29GL128N S29GL256N S29GL512N Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 L L H L L H L L H L L H CE# OE# WE # H
Autoselect Codes, (High Voltage Method)
A22 A14 to to A15 A10 X X A9 A8 to A7 X A6 A5 to A4 X A3 to A2 L L X X VID X L X H H L X X VID X L X H H L X X VID X L X H H SA X VID X L X L A1 A0 DQ8 to DQ15 00 22 22 22 22 22 22 22 22 22 X DQ7 to DQ0
L
L
VID
L
L L H H L H H L H H H
L H L H H L H H L H L
01h 7Eh 23h 01h 7Eh 22h 01h 7Eh 21h 01h 01h (protected), 00h (unprotected) 98h (factory locked), 18h (not factory locked)
Sector Group Protection Verification Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector
L
L
H
X
X
VID
X
L
X
L
H
H
X
L
L
H
X
X
VID
X
L
X
L
H
H
X
88h (factory locked), 08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
Sector Protection
The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue
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using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. The factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the ExpressFlashTM Service. Contact your sales representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Command Sequence" section on page 66 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the old 12V controlled protection method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device will abort the Lock Register back to the default 11 state. The programming time of the Lock Register is same as the typical word programming time without utilizing the Write Buffer of the device. During a Lock Register programming sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the Lock Register has completed to indicate programming status. All Lock Register bits are readable to allow users to verify Lock Register statuses. The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock Register at the same time. This allows users to lock the Secured Silicon Sector and then set the device either permanently into Password Protection Mode or Persistent Protection Mode and then lock the Secured Silicon Sector at separate instances and time frames. Secured Silicon Sector Protection allows the user to lock the Secured Silicon Sector area
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Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the Persistent Protection Mode Password Protection Mode Lock Bit allows the user to set the device permanently to operate in the Password Protection Mode
Table 6.
DQ15-3 Don't Care DQ2
Lock Register
DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit
Password Protection Mode Lock Bit
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Dynamically Locked-The sector is protected and can be changed by a simple command Persistently Locked-A sector is protected and cannot be changed Unlocked-The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYB bits are in the "unprotected state". Each DYB is individually modifiable through the DYB Set Command and DYB Clear Command. When the parts are first shipped, all of the Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all PPB bits are changeable. The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPB bits cleared, the DYB bits control whether or not the sector is protected or unprotected. By issuing the DYB Set and DYB Clear command sequences, the DYB bits will be protected or unprotected, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un-protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a more static, and difficult to change, level of protection. The PPB bits retain their state across power cycles because they are Non-Volatile. Individual PPB bits are set with a program command but must all be cleared as a group through an erase command. The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired settings, the PPB Lock Bit may be set to the "freeze state". Setting the PPB Lock Bit to the "freeze state" disables all program and erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits into their current state. The only way to clear the PPB Lock Bit to the
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"unfreeze state" is to go through a power cycle, or hardware reset. The Software Reset command will not clear the PPB Lock Bit to the "unfreeze state". System boot code can determine if any changes to the PPB bits are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock Bit to disable any further changes to the PPB bits during system operation. The WP# write protect pin adds a final level of hardware protection. When this pin is low it is not possible to change the contents of the WP# protected sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set and DYB Clear commands for the dynamic sectors switch the DYB bits to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be disabled to the "unfreeze state" by either putting the device through a power-cycle, or hardware reset. The PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again to the "freeze state" will lock the PPB bits, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB Lock Bit Set command early in the boot code, and protect the boot code by holding WP# = VIL.
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB is programmed to the protected state through the "PPB Program" command, that sector will be protected from program or erase operations will be read-only. If a PPB requires erasure, all of the sector PPB bits must first be erased in parallel through the "All PPB Erase" command. The "All PPB Erase" command will preprogrammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike programming where individual PPB bits are programmable. The PPB bits have the same endurance as the flash memory. Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the PPB bit or erasing of all PPB bits has completed to indicate programming and erasing status. Erasing all of the PPB bits at once requires typical sector erase time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate that all PPB bits have been erased. Reading the PPB Status bit requires the initial access time of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the "freeze state", the PPB bits cannot be changed. When cleared to the "unfreeze state", the PPB bits are changeable. There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the "un-
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freeze state" after power-up or hardware reset. There is no command sequence to unlock or "unfreeze" the PPB Lock Bit. Configuring the PPB Lock Bit to the freeze state requires approximately 100ns. Reading the PPB Lock Status bit requires the initial access time of the device.
Table 7.
Protection States DYB Bit Unprotect Unprotect Unprotect Unprotect Protect Protect Protect Protect PPB Bit Unprotect Unprotect Protect Protect Unprotect Unprotect Protect Protect
Sector Protection Schemes
Sector State Unprotected - PPB and DYB are changeable Unprotected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable
PPB Lock Bit Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze
Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB bit is set, and the PPB Lock Bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the PPB Lock Bit to "unfreeze state". If the PPB bit is cleared, the sector can be dynamically locked or unlocked. The DYB bit then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sector can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock Status Read commands to the device. The Autoselect Sector Protection Verification outputs the OR function of the DYB bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit is a 1, the sector is either protected by DYB or PPB or both. When the OR function of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed, the Persistent Protection Mode Lock Bit prevents programming of the Password Protection Mode Lock Bit. This guarantees that a hacker could not place the device in Password Protection Mode. The Password Protection Mode Lock Bit resides in the "Lock Register".
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Password Sector Protection
The Password Sector Protection method allows an even higher level of security than the Persistent Sector Protection method. There are two main differences between the Persistent Sector Protection and the Password Sector Protection methods: When the device is first powered on, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. The only means to clear and unfreeze the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region outside of the flash memory. Once the Password Protection Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared to the "unfreezed state", and the PPB bits can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check" after the valid 64-bit password has been entered for the PPB Lock Bit to be cleared to the "unfreezed state". This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first program the password. The factory recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Read operations. Once the desired password is programmed in, the customer must then set the Password Protection Mode Lock Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when programming the Password Protection Mode Lock Bit. More importantly, the user must be sure that the password is correct when the Password Protection Mode Lock Bit is programmed. Due to the fact that read operations are disabled, there is no means to read what the password is afterwards. If the password is lost after programming the Password Protection Mode Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Password Protection Mode Lock Bit, once programmed, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Protection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is
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programmed, the Persistent Protection Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Password Read commands. The password function works in conjunction with the Password Protection Mode Lock Bit, which when programmed, prevents the Password Read command from reading the contents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the Password Protection Mode Lock Bit after power-up reset. If the Password Protection Mode Lock Bit is also programmed after programming the Password, the Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit after a hardware reset (RESET# asserted) or a power-up reset. Successful execution of the Password Unlock command clears and unfreezes the PPB Lock Bit, allowing for sector PPB bits to be modified. Without issuing the Password Unlock command, while asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the "freeze state". If the Password Protection Mode Lock Bit is not programmed, the device defaults to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit is cleared to the "unfreeze state" after power-up or hardware reset. The PPB Lock Bit is set to the "freeze state" by issuing the PPB Lock Bit Set command. Once set to the "freeze state" the only means for clearing the PPB Lock Bit to the "unfreeze state" is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Reading the PPB Lock Bit requires a 200ns access time.
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a "0." The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a "1." Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
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The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range 000000h-000007h Determined by customer 000008h-00007Fh Unavailable Customer Lockable ESN Factory Locked ESN ExpressFlash Factory Locked ESN or determined by customer Determined by customer
The system accesses the Secured Silicon Sector through a command sequence (see "Write Protect (WP#)"). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte Secured Silicon sector. The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See "Command Definitions" . Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h-000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices. Customers may opt to have their code programmed by the factory through the ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from the factory with the Secured Silicon Sector permanently locked. Contact your sales representative for details on using the ExpressFlash service.
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in"Advanced Sector Protection" section on page 54. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics" section on page 90. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 12 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
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then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your sales representative for copies of these documents.
Table 8.
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 9.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 10.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 001Ah 0019h 0018h 0002h 0000h 0005h 0000h 0001h 00xxh 000xh 0000h 000xh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size = 2N byte 1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 00FFh, 001h, 0000h, 0002h = 512 Mb 00FFh, 0000h, 0000h, 0002h = 256 Mb 007Fh, 0000h, 0000h, 0002h = 128 Mb
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 11.
Addresses (x16) 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 0010h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 0008h = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV WP# Protection 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh
0002h 0001h 0000h 0008h 0000h 0000h 0002h 00B5h 00C5h
4Fh
00xxh
50h
0001h
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
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Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations-"AC Characteristics" section provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirements. This method is an alternative to that shown in Table 5, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an
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address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: A read cycle at address XX00h returns the manufacturer code. Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 12 shows the address and data requirements for both command sequences. See also "Secured Silicon Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified programming method. For such application requirements, please contact your
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local Spansion representative. Word programming is supported for backward compatibility with existing Flash driver software and for occasional writing of individual words. Use of Write Buffer Programming is strongly recommended for general programming use when more than a few words are to be programmed. The effective word programming time using Write Buffer Programming is much shorter than the single word programming time. Any word cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 12).
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-A4. All subsequent address/ data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.)
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Note that if a Write Buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. This flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. For applications requiring incremental bit programming, a modified programming method is required, please contact your local Spansion representative. Any bit in a write buffer address range cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
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be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Figure 2 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations-"AC Characteristics" section for parameters, and Figure 14 for timing diagrams.
Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= "1", then the device FAILED. If this flowchart location was reached because DQ1= "1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the WriteBuffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. 4. See Table 12 for command sequences required for write buffer programming.
Read DQ15 - DQ0 at Last Loaded Address
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ15 - DQ0 with address = Last Loaded Address No
Yes
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Figure 1.
Write Buffer Programming Operation
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START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 12 for program command sequence.
Figure 2.
Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5s typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. Note that the Secured Silicon Sector autoselect, and CFI functions are unavailable when program operation is in progress. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
Program Operation or Write-to-Buffer Sequence in Progress
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Wait 15 s
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h
Write Program Resume Command Sequence
Device reverts to operation prior to Program Suspend
Figure 3.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits.
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Any commands written during the chip erase operation are ignored, including erase suspend commands. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. Refer to the "Erase And Programming Performance" section on page 102 in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 12 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
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START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 12 for program command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 4.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the pro-
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the "Autoselect Mode" section and "Autoselect Command Sequence" section on page 66 sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. It is important to allow an interval of at least 5 ms between Erase Resume and Erase Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the Secured Silicon Sector Protection Bit, Persistent Protection Mode Lock Bit, and Password Protection Mode Lock Bit. The Lock Register bits are all readable after an initial access delay. The Lock Register Command Set Entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. Note that issuing the Lock Register Command Set Entry command disables reads and writes for the flash memory. Lock Register Program Command Lock Register Read Command The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode. Otherwise the device will hang. If this happens, the flash device must be reset. Please refer to RESET# for more information. It is important to note that the device will be in either Persistent Protection mode or Password Protection mode depending on the mode selected prior to the device hang. For either the Secured Silicon Sector to be locked, or the device to be permanently set to the Persistent Protection Mode or the Password Protection Mode, the associated Lock Register bits must be programmed. Note that the Persistent Protection Mode Lock Bit and Password Protection Mode Lock Bit can never be programmed together at the same time. If so, the Lock Register Program operation will abort. The Lock Register Command Set Exit command must be initiated to reenable reads and writes to the main memory.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. The Password Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Password Protection Command Set Entry command disabled reads and writes the main memory.
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Password Program Command Password Read Command Password Unlock Command The Password Program command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special addressing order required for programming the password. The password is programmed in 8-bit or 16-bit portions. Each portion requires a Password Program Command. Once the Password is written and verified, the Password Protection Mode Lock Bit in the "Lock Register" must be programmed in order to prevent verification. The Password Program command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. The Password Read command is used to verify the Password. The Password is verifiable only when the Password Protection Mode Lock Bit in the "Lock Register" is not programmed. If the Password Protection Mode Lock Bit in the "Lock Register" is programmed and the user attempts to read the Password, the device will always drive all F's onto the DQ databus. The lower two address bits (A1-A0) for word mode and (A1-A-1) for by byte mode are valid during the Password Read, Password Program, and Password Unlock commands. Writing a "1" to any other address bits (AMAX-A2) will abort the Password Read and Password Program commands. The Password Unlock command is used to clear the PPB Lock Bit to the "unfreeze state" so that the PPB bits can be modified. The exact password must be entered in order for the unlocking function to occur. This 64-bit Password Unlock command sequence will take at least 2 s to process each time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match the password. If another password unlock is issued before the 64-bit password check execution window is completed, the command will be ignored. If the wrong address or data is given during password unlock command cycle, the device may enter the write-tobuffer abort state. In order to exit the write-to-abort state, the write-tobuffer-abort-reset command must be given. Otherwise the device will hang. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit to the "unfreeze state". The password is 64 bits long. A1 and A0 are used for matching. Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10, and A1-A0=11 if the device is configured to operate in word mode. Approximately 2 s is required for unlocking the device after the valid 64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to re-lock the device into the Password Protection Mode, the PPB Lock Bit Set command can be re-issued.
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The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing the Password Protection Command Set Exit command reenables reads and writes for the main memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits (PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits). The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and writes for the main memory. PPB Program Command The PPB Program command is used to program, or set, a given PPB bit. Each PPB bit is individually programmed (but is bulk erased with the other PPB bits). The specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22A16 for S29GL128N) is written at the same time as the program command. If the PPB Lock Bit is set to the "freeze state", the PPB Program command will not execute and the command will time-out without programming the PPB bit. All PPB Erase Command The All PPB Erase command is used to erase all PPB bits in bulk. There is no means for individually erasing a specific PPB bit. Unlike the PPB program, no specific sector address is required. However, when the All PPB Erase command is issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to "freeze state", the ALL PPB Erase command will not execute and the command will time-out without erasing the PPB bits. The device will preprogram all PPB bits prior to erasing when issuing the All PPB Erase command. Also note that the total number of PPB program/erase cycles has the same endurance as the flash memory array. PPB Status Read Command The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device. This requires an initial access time latency. The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for the main memory.
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and reading the logic state of the PPB Lock Bit. The Global Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution.
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Reads and writes from the main memory are not allowed. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock Bit to the "freeze state" if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set to the "freeze state", it cannot be cleared unless the device is taken through a power-on clear (for Persistent Protection Mode) or the Password Unlock command is executed (for Password Protection Mode). If the Password Protection Mode Lock Bit is programmed, the PPB Lock Bit status is reflected as set to the "freeze state", even after a power-on reset cycle. PPB Lock Bit Status Read Command The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read command to the device. The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB) to the "protected state", clear the Dynamic Protection Bit (DYB) to the "unprotected state", and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes from main memory. DYB Set Command DYB Clear Command The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for a given sector. The high order address bits are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYB bits are modifiable at any time, regardless of the state of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the "unprotected state" at power-up or hardware reset.
--DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing a DYB Status Read command to the device. This requires an initial access delay. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes to the main memory.
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Secured Silicon Sector Entry Command
The Secured Silicon Sector Entry command allows the following commands to be executed Read from Secured Silicon Sector Program to Secured Silicon Sector Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command has to be issued to exit Secured Silicon Sector Mode.
Secured Silicon Sector Exit Command
The Secured Silicon Sector Exit command may be issued to exit the Secured Silicon Sector Mode.
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Command Definitions
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16
Cycles Bus Cycles (Notes 2-5) First Addr RA XXX 555 555 Data RD F0 AA AA 2AA 2AA 55 55 555 555 90 90 X00 X01 (SA) X02 X03 01 227E XX00 XX01 Note 10 X0E Note 17 X0F Note 17 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Command (Notes)
Read (6) Reset (7) Manufacturer ID Autoselect (Note 8) Device ID
1 1 4 4
Sector Protect Verify
4
555
AA
2AA
55
555
90
Secure Device Verify (9)
4 1 4 3 1 3 3 2 2 2 2 6 6 1 1
555 55 555 555 SA 555 555 XXX XXX XXX XXX 555 555 XXX XXX
AA 98 AA AA 29 AA AA A0 80 80 90 AA AA B0 30
2AA
55
555
90
CFI Query (11) Program Write to Buffer Program Buffer to Flash (confirm) Write-to-Buffer-Abort Reset (16) Unlock Bypass Unlock Bypass Program (12) Unlock Bypass Sector Erase (12) Unlock Bypass Chip Erase (12) Unlock Bypass Reset (13) Chip Erase Sector Erase Erase Suspend/Program Suspend (14) Erase Resume/Program Resume (15)
2AA 2AA
55 55
555 SA
A0 25
PA SA
PD WC PA PD WBL PD
2AA 2AA PA SA XXX XXX 2AA 2AA
55 55 PD 30 10 00 55 55
555 555
F0 20
555 555
80 80
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
Sector Command Definitions
Secured Silicon SEctor Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88
Secured Silicon Sector Exit (18)
4
555
AA
2AA
55
555
90
XX
00
Lock Register Command Set Definitions
Lock Register Lock Register Command Set Entry Lock Register Bits Program (22) Lock Register Bits Read (22) Lock Register Command Set Exit (18, 23) 3 2 1 2 555 XXX 00 XXX AA A0 Data 90 XXX 00 2AA XXX 55 Data 555 40
Password Protection Command Set Definitions
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Cycles
Bus Cycles (Notes 2-5) First Addr 555 XXX XXX 00 00 Data AA A0 PWD 0 25 29 90 XXX 00 Second Addr 2AA PWA x 01 00 Data 55 PWD x PWD 1 03 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 Third Addr 555 Data 60 Fourth Addr Data Fifth Addr Data Sixth Addr Data
Command (Notes)
Password Protection Command Set Entry Password Program (20) Password Password Read (19)
3 2 4
Password Unlock (19)
7
Password Protection Command Set Exit (18, 23)
2
XXX
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command Set Entry PPB Program (24, 25) PPB All PPB Erase PPB Status Read (25) Non-Volatile Sector Protection Command Set Exit (18) 3 2 2 1 2 555 XXX XXX SA XXX AA A0 80 RD (0) 90 XXX 00 2AA SA 00 55 00 30 555 C0
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection Freeze Command Set Entry PPB Lock Bit PPB Lock Bit Set (25) PPB Lock Status Read (25) Global Non-Volatile Sector Protection Freeze Command Set Exit (18) 3 2 1 2 555 XXX XXX XXX AA A0 RD (0) 90 XXX 00 2AA XXX 55 00 555 50
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set Entry DYB Set (24, 25) DYB DYB Clear (25) DYB Status Read (25) Volatile Sector Protection Command Set Exit (18) 3 2 2 1 2 555 XXX XXX SA XXX AA A0 A0 RD (0) 90 XXX 00 2AA SA SA 55 00 01 555 E0
Legend: X = Don't care RA = Address of the memory to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax-A16 uniquely select any sector. WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
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WC = Word Count is the number of write buffer locations to load minus 1. PWD = Password PWDx = Password word0, word1, word2, and word3. DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.). 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here. 10. The data value for DQ7 is "1" for a serialized and protected OTP region and "0" for an unserialized and unprotected Secured Silicon Sector region. See "Secured Silicon Sector Flash Memory Region" for more information. For S29GLxxxNH: XX18h/18h = Not Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory Locked. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command. 13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes. 16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode. 17. S29GL512NH/L = 2223h/23h, 2201h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/ 01h. 18. The Exit command returns the device to reading the array. 19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. For PWDx, only one portion of the password can be programmed per each "A0" command. 21. The All PPB Erase command embeds programming of all PPB bits before erasure. 22. All Lock Register bits are one-time programmable. Note that the program state = "0" and the erase state = "1". Also note that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that are reserved for future use will default to "1's". The Lock Register is shipped out as "FFFF's" before Lock Register Bit program execution. 23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise the device will hang. 24. If ACC = VHH, sector protection will match when ACC = VIH 25. Protected State = "00h", Unprotected State = "01h".
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Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. Note that all Write Operation Status DQ bits are valid only after 4 s delay.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. Table 13 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 17 in the AC Characteristics section shows the Data# Polling timing diagram.
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START
Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1
Yes Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 13 shows the outputs for RY/BY#.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 13 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
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START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command
No
Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 6.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the
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read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 and Figure 19 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
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the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write Buffer section for more details.
Table 13.
Status Standard Mode Program Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm ProgramSuspend Read Program-Suspended Sector Non-Program Suspended Sector Erase-Suspended Sector Non-Erase Suspended Sector
Write Operation Status
DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/ BY# 0 0 1 1 N/A Data Toggle N/A 1 1 N/A N/A N/A N/A N/A N/A N/A 0 1 0 0 0
DQ7 (Note 2) DQ7# 0
Invalid (not allowed) Data 1 No toggle 0
Erase Suspend Mode
EraseSuspend Read
Erase-Suspend-Program (Embedded Program) Write-toBuffer
Notes:
DQ7# DQ7# DQ7#
Toggle Toggle Toggle
0 0 0
Busy (Note 3) Abort (Note 4)
1. DQ5 switches to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to `1' when the device has aborted the write-to-buffer operation.
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Absolute Maximum Ratings
A9, OE#, and ACC (Note 5) . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5V
5. Minimum DC input voltage on pins A9, OE#, and ACC is
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
20 ns
Figure 7.
Figure 8. Maximum Positive Overshoot Waveform
Operating Ranges
Notes: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See "Product Selector Guide" section on page 19.
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DC Characteristics
CMOS Compatible-S29GL128N, S29GL256N, S29GL512N
Parameter Symbol ILI ILIT ILO Parameter Description (Notes) Input Load Current (1) A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, VCC = VCCmax, f = 5 MHz ICC1 VCC Active Read Current (1) CE# = VIL, OE# = VIH, VCC = VCCmax, f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCCmax f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCCmax, f=33 MHz 30 60 1 5 50 1 Min Typ Max WP/ACC: 2.0 Others: 1.0 35 1.0 50 90 10 mA 20 80 5 mA mA Unit
A A A
mA
ICC2
VCC Intra-Page Read Current (1)
ICC3 ICC4
VCC Active Erase/Program Current (2, 3) CE# = VIL, OE# = VIH, VCC = VCCmax VCC Standby Current CE#, RESET# = VSS 0.3 V, OE# = VIH, VCC = VCCmax VIL = VSS + 0.3 V/0.1V VCC = VCCmax; VIL = VSS + 0.3 V/-0.1V, RESET# = VSS 0.3 V VCC = VCCmax VIH = VCC 0.3 V, VIL = VSS + 0.3 V/-0.1V, WP#/ACC = VIH CE# = VIL, OE# = VIH, VCC = VCCmax, WP#/ACC = VIH WP#/ACC pin VCC pin -0.1 0.7 x VIO VCC = 2.7 -3.6 V VCC = 2.7 -3.6 V IOL = 100 A IOH = -100 A 0.85 x VIO 2.3 11.5 11.5
ICC5
VCC Reset Current
1
5
A
ICC6
Automatic Sleep Mode (4)
1
5
A
IACC
ACC Accelerated Program Current
10 50
20 80 0.3 x VIO VIO + 0.3 12.5 12.5 0.15 x VIO
mA
VIL VIH VHH VID VOL VOH VLKO
Input Low Voltage (5) Input High Voltage (5) Voltage for ACC Erase/Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage (5) Output High Voltage (5) Low VCC Lock-Out Voltage (3)
V V V V V V
2.5
V
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress. 3. Not 100% tested. 4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns. 5. VIO = 1.65-1.95 V or 2.7-3.6 V 6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
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Test Conditions
Table 14.
3.3 V
Test Specifications
All Speeds 1 TTL gate 30 5 0.0-VIO 0.5VIO 0.5 VIO pF ns V V V Unit
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels
Device Under Test CL 6.2 k
2.7 k
Note: Diodes are IN3064 or equivalent.
Figure 9.
Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
Key to Switching Waveforms
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs
VIO 0.0 V
Input
0.5 VIO
Measurement Level
0.5 VIO V
Output
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 10.
Input Waveforms and Measurement Levels
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AC Characteristics
Read-Only Operations-S29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV Std. tRC Description Read Cycle Time Address to Output Delay (Note 2) Chip Enable to Output Delay (Note 3) Test Setup VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V Min Speed Options 90 90 100 110 110 Unit 100 110 110 90 100 110 110 90 100 110 110 25 25 25 25 20 20 0 0 10 35 25 35 30 35 ns
tAVQV
tACC
Max
ns
tELQV
tCE
Max Max Max Max Max Min Min Min Min
ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and Data# Polling
tOEH tCEH
Notes:
Chip Enable Hold Time Read
1. Not 100% tested. 2. CE#, OE# = VIL 3. OE# = VIL 4. See Figure 9 and Table 14 for test specifications. 5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
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AC Characteristics
tRC Addresses CE# tCEH tRH tRH OE# tOEH WE# HIGH Z tCE tOH Output Valid HIGH Z tOE tDF Addresses Stable tACC
Outputs RESET# RY/BY#
0V
Figure 11.
Read Operation Timings
Amax-A2
Same Page
A2-A0*
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Qa
Qb
Qc
Qd
Notes: 1. Figure shows word mode.
Figure 12.
Page Read Timings
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AC Characteristics
Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min Speed (Note 2) 20 500 500 50 20 0 Unit ns ns ns ns s ns
Notes: 1. Not 100% tested. If ramp rate is equal to or faster than 1V/100s with a falling edge of the RESET# pin initiated, the RESET# pin needs to be held low only for 100s for power-up. 2. Next generation devices may have different reset speeds.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP tRH
Figure 13.
Reset Timings
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AC Characteristics
Erase and Program Operations-S29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tCEPH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High during toggle bit polling Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) tVHH tVCS tBUSY VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Erase/Program Valid to RY/BY# Delay Per Word Per Word Word Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Min Min Min 90 90 Speed Options 100 100 0 15 45 0 45 0 20 20 0 0 0 35 30 240 15 13.5 60 54 0.5 250 50 90 ns ns ns ns ns ns s s s s s sec ns s ns 110 110 110 110 Unit ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
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AC Characteristics
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Read Status Data (last two cycles)
PA
PA
tCH
tWHWH1 tWPH
A0h
Status
DOUT tRB
Figure 14.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 15.
Notes: 1. Not 100% tested. 2. CE#, OE# = VIL 3. OE# = VIL
Accelerated Program Timing Diagram
4. See Figure 9 and Table 14 for test specifications.
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AC Characteristics
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE# tCH tWP WE# tCS tDS tDH Data 55h 30h
10 for Chip Erase In Progress Complete
OE#
tWPH
tWHWH2
tBUSY RY/BY# tVCS VCC
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (. 2. These waveforms are for the word mode.
tRB
Figure 16.
Chip/Sector Erase Operation Timings
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AC Characteristics
tRC Addresses VA tACC CE# tCH OE# tOEH WE# tOH DQ7
Complement Complement True Valid Data
High Z
VA
VA
tCE
tOE tDF
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
High Z
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
Figure 17.
Data# Polling Timings (During Embedded Algorithms)
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AC Characteristics
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ2 and DQ6 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 18.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program
Erase Resume Erase Erase Complete
Erase Suspend Read
Erase Erase Suspend Suspend Read Program
DQ6
DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 19.
DQ2 vs. DQ6
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AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV tAVWL Std. tWC tAS TASO tELAX tAH tAHT tDVEH tEHDX tDS tDH tCEPH tOEPH tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High during toggle bit polling OE# High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Notes: 1. Not 100% tested. 2. See the "AC Characteristics" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Unless otherwise indicated, AC specifications for 90 ns, 100ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
Speed Options 90 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ 90 100 100 0 15 45 0 45 0 20 20 0 0 0 35 30 240 110 110 110 110 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Per Word
Typ
15
s
Per Word Word Word
Typ Typ Typ Typ
13.5 60 54 0.5
s s s sec
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AC Characteristics
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7# DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 20.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
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Erase And Programming Performance
Parameter Sector Erase Time S29GL128N Chip Erase Time S29GL256N S29GL512N Total Write Buffer Programming Time (Note 3) Total Accelerated Effective Write Buffer Programming Time (Note 3) S29GL128N Chip Program Time S29GL256N S29GL512N Typ (Note 1) 0.5 64 128 256 240 Max (Note 2) 3.5 256 512 1024 s sec Unit sec Excludes 00h programming prior to erasure (Note 5) Comments
200 123 246 492
s
Excludes system level overhead (Note 6)
sec
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 10,000 cycles, checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol CIN Parameter Description Input Capacitance Test Setup VIN = 0 TSOP BGA TSOP BGA TSOP BGA Typ 6 4.2 8.5 5.4 7.5 3.9 Max 7.5 5.0 12 6.5 9 4.7 Unit pF pF pF pF pF pF
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
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CellularRAM Type 2
128/64/32 Megabit Burst CellularRAM
Features
Single device supports asynchronous, page, and burst operations VCC Voltages
-- 1.70V-1.95V VCC
Random Access Time: 70ns Burst Mode Write Access
-- Continuous burst
Burst Mode Read Access
-- 4, 8, or 16 words, or continuous burst
Page Mode Read Access
-- Sixteen-word page size -- Interpage read access: 70ns -- Intrapage read access: 20ns
Low Power Consumption
-- Asynchronous READ < 25mA -- Intrapage READ < 15mA -- Initial access, burst READ < 35mA -- Continuous burst READ < 11mA -- Standby: 180A -- Deep power-down < 10A
Low-Power Features
-- Temperature Compensated Refresh (TCR) On-chip sensor control -- Partial Array Refresh (PAR) -- Deep Power-Down (DPD) Mode
General Description
CellularRAMTM products are high-speed, CMOS dynamic random access memories developed for low-power, portable applications. These devices include an industry standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate smoothly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only
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that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) adjusts the refresh rate to match the device temperature-- the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the RCR.
128M: A[22:0] 64M: A[21:0] 32M: A[20:0]
Address Decode Logic
DRAM MEMORY ARRAY
Input/ Output MUX and Buffers
DQ[7:0]
Refresh Configuration Register (RCR)
DQ[15:8]
Bus Configuration Register (BCR)
CE# WE# OE# CLK ADV# CRE WAIT LB# UB#
Control Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information.
Figure 21.
Functional Block Diagram
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Table 15.
Symbol 128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Type Input
Signal Descriptions
Description
Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Device Power Supply: (1.7V-1.95V) Power supply for device core operation. I/O Power Supply: (1.7V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground.
CLK
Input
ADV# CRE CE# OE# WE# LB# UB# DQ[15:0]
Input Input Input Input Input Input Input Input/ Output
WAIT
Output
VCC VCCQ VSS VSSQ
Supply Supply Supply Supply
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and page mode operations.
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Table 16.
MODE Read Write Standby No Operation Configuration Register DPD POWER Active Active Standby Idle Active Deep Power-down
Bus Operations--Asynchronous Mode
CE# L L H L L H OE# L X X X H X WE# H L X X L X CRE L L L L H X LB#/ UB# L L X X X X WAIT (Note 2) Low-Z Low-Z High-Z Low-Z Low-Z High-Z DQ[15:0] (Note 3) Data-Out Data-In High-Z X High-Z High-Z 7 NOTES 4 4 5, 6 4, 6
CLK (Note 1) ADV# X X X X X X L L X X L X
Notes: 1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained until RCR is reconfigured.
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Table 17.
MODE Async Read Async Write Standby No Operation Initial Burst Read Initial Burst Write Burst Continue Burst Suspend Configuration Register DPD POWER Active Active Standby Idle Active Active Active Active Active Deep Power-Down X X CLK (Note 1) ADV# X X X X L L X X L L H X L X
Bus Operations--Burst Mode
CE# L L H L L L L L L H OE# L X X X X H X H H X WE# H L X X H L X X L X CRE L L L L L L L L H X LB#/ UB# L L X X L X X X X X WAIT (Note 2) Low-Z Low-Z High-Z Low-Z Low-Z Low-Z Low-Z Low-Z Low-Z High-Z DQ[15:0] (Note 3) Data-Out Data-In High-Z X Data-Out Data-In Data-In or Data-Out High-Z High-Z High-Z NOTES 4 4 5, 6 4, 6 4, 8 4, 8 4, 8 4, 8 8 7
Notes: 1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 18 and Table 22). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation.
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VCC VCCQ
VCC = 1.7 V
tPU > 150 s Device Initialization
Device ready for normal operation
Figure 22.
Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 23) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 24) occur when CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/ WRITE operation. During asynchronous operation, the CLK input must be held static (HIGH or LOW, no transitions). WAIT will be driven while the device is enabled and its state should be ignored.
CE#
OE# WE# ADDRESS Address Valid
DATA
Data Valid
LB#/UB#
tRC = READ Cycle Time Don't Care
Note: ADV must remain LOW for page mode operation.
Figure 23.
READ Operation (ADV# LOW)
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CE#
OE#
WE#
ADDRESS
Address Valid
DATA
Data Valid
LB#/UB#
tWC = WRITE Cycle Time Don't Care
Figure 24.
WRITE Operation (ADV# LOW)
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 25 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable page mode functionality. ADV must be driven LOW during all page mode read accesses.
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CE#
OE# WE# ADDRESS ADD[0] ADD[1] ADD[2] ADD[3]
tAA DATA
tAPA D[0]
tAPA D[1]
tAPA D[2] D[3]
LB#/UB#
Don't Care
Figure 25.
Page Mode READ Operation (ADV# LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 26) or WRITE (WE# = LOW, Figure 27). The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. WAIT will again be asserted if the burst crosses a row boundary. Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be deasserted and the burst can continue (see Figure 47). To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time during burst operations. If a burst suspension will
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cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
CLK A[22:0] ADV# Address Valid
Latency Code 2 (3 clocks), variable CE# OE# WE# WAIT DQ[15:0] LB#/UB# D[0] D[1] D[2] D[3]
READ Burst Identified (WE# = HIGH)
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 26.
Burst Mode READ (4-word burst)
CLK A[22:0] ADV# Address Valid
Latency Code 2 (3 clocks), variable CE# OE# WE# WAIT DQ[15:0] LB#/UB# D[0] D[1] D[2] D[3]
WRITE Burst Identified (WE# = LOW)
Legend:
Don't care
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 27.
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Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 55 for the "Asynchronous WRITE Followed by Burst READ" timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 28 below). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
External Pull-Up/ Pull-Down Resistor
CellularRAM WAIT READY WAIT Processor Other Device WAIT Other Device
Figure 28.
Wired or WAIT Configuration
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT signal asserts.) When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ or WRITE operations launched while an on-chip refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional clock cycles until the refresh has completed (see Figure 29 and Figure 30). When the refresh operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses the boundary between 128-word rows. The WAIT assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations.
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LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
CLK
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL High-Z Address Valid
A[22:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 29.
Refresh Collision During READ Operation
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CLK
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL High-Z Address Valid
A[22:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 30.
Refresh Collision During WRITE Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires increasingly frequent refresh operation to maintain data integrity as temperatures increase. More frequent refresh is required due to increased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. For example, if the case temperature is 50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
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Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 23). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state.
Access Using CRE
The configuration registers can be written to using either a synchronous or an asynchronous operation when the configuration register enable (CRE) input is HIGH (see Figure 31 and Figure 32). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are written via address pins A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. For reads, address inputs other than A[19] are "Don't Care," and register bits 15:0 are output on DQ[15:0].
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A[22:0] (except A19)
OPCODE tAVS Select Control Register tAVH
ADDRESS
A19 (Note)
ADDRESS
CRE tAVS tAVH tVPH ADV# tVP tCBPH Initiate Control Register Access CE# tCW
OE# tWP Write Address Bus Value to Control Register WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
Figure 31.
Configuration Register WRITE, Asynchronous Mode Followed by READ
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CLK Latch Control Register Value A[22:0] (except A19) OPCODE tHD tSP A19 (Note 2) tSP CRE tHD tSP ADV# tHD tCSP CE# Latch Control Register Address ADDRESS ADDRESS
tCBPH (Note 3)
OE# tSP WE# tHD LB#/UB# tCEW WAIT High-Z DQ[15:0] High-Z DATA VALID
Legend:
Don't care
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
Figure 32.
Configuration Register WRITE, Synchronous Mode Followed by READ0
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Table 18 below describes the control bits in the BCR. At power up, the BCR is set to 9D4Fh.
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The BCR is accessed using CRE and A[19] HIGH.
Table 18.
A[22:20] A19 A[18:16] A15 A14
Bus Configuration Register Definition
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
22-20
19
18-16
15
14
13
12
11
10
9
8 WAIT Configuration (WC)
7
6
5
4
3 Burst Wrap (BW) (Note)
2
1
0
Reserved
Register Select
Reserved
Operating Mode
Initial Latency
Latency Counter
WAIT Polarity
Reserved
Reserved
Reserved
Output Impedance
Burst Length (BL) (Note)
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0" Setting is ignored BCR[5] BCR[4] 0 0 1 1 0 1 0 1 Output Impedance Full Drive (default) 1/2 Drive 1/4 Drive Reserved
BCR[13] BCR[12] BCR[11] Latency Counter 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Code 0-Reserved Code 1-Reserved Code 2 Code 3 (Default) Code 4 Code 5 Code 6 Code 7-Reserved BCR[8] 0 1 BCR[10] WAIT Polarity 0 1 BCR[15] 0 1 BCR[19] 0 1 Register Select Select RCR Select BCR Operating Mode Synchronous burst access mode Asynchronous access mode (default) Active LOW Active HIGH (default) BCR[2] BCR[1] BCR[0] Burst Length (Note) 0 0 0 1 0 1 1 1 Others 1 0 1 1 4 words 8 words 16 words Continuous burst (default) Reserved WAIT Configuration Asserted during delay Asserted one data cycle before delay (default) BCR[3] 0 1 Burst Wrap (Note) Burst wraps within the burst length Burst no wrap (default)
Note: Burst wrap and length apply to READ operations only.
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Table 19.
STARTING ADDRESS (DECIMAL)
0 1 2 3 4
Sequence and Burst Length
CONTINUOUS BURST LINEAR
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
BURST WRAP BCR[3] WRAP
4-WORD BURST LENGTH LINEAR
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
8-WORD BURST LENGTH LINEAR
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-WORD BURST LENGTH LINEAR
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0
Yes
5 6 7 ... 14 15 0 1 2 3 4 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 ... 14-15-16-17-18-19-...-23-24-25-26-27-28-29 5-16-17-18-19-20-...-24-25-26-27-28-29-30
1
No
5 6 7 ... 14 15
Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ operations. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1 overrides the burst-length setting.
Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word READ burst wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the burst goes past the last address. Enabling burst nowrap (BCR[3] = 1) overrides the burst-length setting.
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Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Normal output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at full drive strength during testing.
Table 20.
BCR[5] 0 0 1 1
Output Impedance
BCR[4] 0 1 0 1 DRIVE STRENGTH Full 1/2 1/4 Reserved
WAIT Configuration (BCR[8]): Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figure 33 and Figure 35). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (Figure 34).
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pulldown resistor to maintain the de-asserted state.
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 35.
Figure 33.
WAIT Configuration (BCR[8] = 0)
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CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 35.
Figure 34.
WAIT Configuration (BCR[8] = 1)
CLK
WAIT
BCR[8] = 0 DATA VALID IN CURRENT CYCLE BCR[8] = 1 DATA VALID IN NEXT CYCLE
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: WAIT active LOW.
Figure 35.
WAIT Configuration During Burst Operation
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Latency codes from two (three clocks) to six (seven clocks) are allowed (see Table 21 and Figure 36 below).
Table 21.
Variable Latency Configuration Codes
LATENCY (Note) MAX INPUT CLK FREQUENCY (MHz) 70ns/80 MHz 75 (13.0ns) 80 (12.5ns) 85ns/66 MHz 44 (22.7ns) 66 (15.2ns)
BCR[13:11] 010 011 100
LATENCY CONFIGURATION CODE 2 (3 clocks) 3 (4 clocks)--default 4 (5 clocks)
NORMAL 2 3 4
REFRESH COLLISION 4 6 8
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
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CLK
VIH VIL VIH VIL VIH VIL Code 2 Valid Address
A[21:0]
ADV#
A/DQ[15:0]
VOH VOL Code 3 (Default)
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
A/DQ[15:0]
VOH VOL Code 4
Valid Output
Valid Output
Valid Output
Valid Output
A/DQ[15:0]
VOH VOL
Valid Output
Valid Output
Valid Output
Legend:
Don't care
Undefined
Figure 36.
Latency Counter (Variable Initial Latency, No Refresh Collision)
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 22 below describes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE and A[19] LOW.
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Table 22.
A[22:20] A19 A[18:8]
Refresh Configuration Register Mapping
A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
22-20 Reserved
19 Register Select
18-8 Reserved
7 Page
6 TCR
5
4 DPD
3 Reserved
2 PAR
1
0
Read Configuration Register
All must be set to "0"
All must be set to "0"
Must be set to "0"
RCR[19] Register Select 0 1 Select RCR Select BCR
RCR[2] RCR[1] RCR[0] 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Refresh Coverage Full array (default) Bottom 1/2 array Bottom 1/4 array Bottom 1/8 array None of array Top 1/2 array Top 1/4 array Top 3/4 array
RCR[7] 0 1
Page Mode Enable/Disable Page Mode Disabled (default) Page Mode Enable
0 1 1 1 1 RCR[4] 0 1
RCR[6] 1 0 0 1
RCR[5] 1 0 1 0
Maximum Case Temp +85C (default) +70C +45C +15C
Deep Power-Down DPD Enable DPD Disable (default)
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three-quarters array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 23 through Table 25).
Table 23.
RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1
128Mb Address Patterns for PAR (RCR[4] = 1)
ACTIVE SECTION Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die ADDRESS SPACE 000000h-7FFFFFh 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 400000h-7FFFFFh 600000h-7FFFFFh 700000h-7FFFFFh SIZE 8 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 4 Meg x 16 2 Meg x 16 1 Meg x 16 DENSITY 128Mb 64Mb 32Mb 16Mb 0Mb 64Mb 32Mb 16Mb
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Table 24.
RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1
64Mb Address Patterns for PAR (RCR[4] = 1)
ACTIVE SECTION Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die ADDRESS SPACE 000000h-3FFFFFh 000000h-2FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 100000h-3FFFFFh 200000h-3FFFFFh 300000h-3FFFFFh SIZE 4 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 DENSITY 64Mb 48Mb 32Mb 16Mb 0Mb 48Mb 32Mb 16Mb
Table 25.
RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1
32Mb Address Patterns for PAR (RCR[4] = 1)
ACTIVE SECTION Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die ADDRESS SPACE 000000h-1FFFFFh 000000h-17FFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 080000h-1FFFFFh 100000h-1FFFFFh 180000h-1FFFFFh SIZE 2 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 DENSITY 32Mb 24Mb 16Mb 8Mb 0Mb 24Mb 16Mb 8Mb
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to "1."
Temperature Compensated Refresh (RCR[6:5]): Default = +85C Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellurlarRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled.
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Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ Relative to VSS . . . . . -0.50V to (4.0V or VCCQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
*Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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DC Characteristics
Table 26.
Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled
Electrical Characteristics and Operating Conditions
Conditions VCC VCCQ VIH VIL VOH VOL ILI ILO Operating Current W: 1.8V J: 1.5V Symbol Min 1.70 1.70 1.35 VCCQ - 0.4 -0.20 0.80 VCCQ 0.20 VCCQ 1 1 Max 1.95 1.95 1.65 VCCQ + 0.2 0.4 Units V V V V V V V A A 2 3 4 4 Notes
Asynchronous Random READ
-70 VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 -85 -70 -85 80 MHz VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 66 MHz 80 MHz 66 MHz VIN = VCCQ or 0V Chip Enabled ICC2 -70 -85 128 M
25 20 15 12 35 30 18 15 25 20 180 120 110 A 6 mA mA 5 mA 5
Asynchronous Page READ
Initial Access, Burst READ
Continuous Burst READ
WRITE Operating Current
Standby Current
VIN = VCCQ or 0V CE# = VCCQ
ISB
64 M 32 M
Notes: 1. Wireless Temperature (-25C < TC < +85C); Industrial Temperature (-40C < TC < +85C). 2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. 4. BCR[5:4] = 00b. 5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. To achieve low standby current, all inputs must be driven to either VCCQ or VSS.
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Table 27.
Temperature Compensated Refresh Specifications and Conditions
Max Case Temperature +85C 64 Mb +70C +45C +15C +85C 32 Mb +70C +45C +15C Standard Power (No Desig.) 120 105 85 70 110 95 80 70 A
Description
Conditions
Symbol
Density
Units
Temperature Compensated Refresh Standby Current
VIN = VCCQ or 0V, CE# = VCCQ
ITCR
Note: IPAR (MAX) values measured with TCR set to 85C.
Table 28.
Partial Array Refresh Specifications and Conditions
Array Partition Full 1/2 64 Mb 1/4 1/8 0 Standard Power (No Desig.) 120 115 110 105 70 110 105 100 95 70 180 50 A
Description
Conditions
Symbol
Density
Units
Partially Array Refresh Standby Current
VIN = VCCQ or 0V, CE# = VCCQ
IPAR 32 Mb
Full 1/2 1/4 1/8 0 128 Mb Full 0
Note:IPAR (MAX) values measured with TCR set to 85C.
Table 29.
Description Deep Power-down
Deep Power-Down Specifications
Symbol IZZ Typ 10 Units A
Conditions VIN = VCCQ or 0V; +25C; VCC = 1.8V
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AC Characteristics
VCC Q Input (Note 1) VSS VCCQ /2 (Note 2) Test Points VCCQ/2 (Note 3) Output
Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2.
Figure 37.
AC Input/Output Reference Waveform
VCCQ R1 DUT 30pF R2 Test Point
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 38. Table 30.
VCCQ 1.8V
Output Load Circuit Output Load Circuit
R1/R2 2.7K
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Table 31.
Asynchronous READ Cycle Timing Requirements
85ns/66 MHz 70ns/80 MHz Min Max 70 70 20 5 10 85 8 10 5 4 1 7.5 85 10 8 10 20 5 8 5 25 85 10 10 5 20 70 10 10 5 8 10 20 10 8 1 10 5 4 7.5 70 70 8 ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns 4 3 4 3 2 4 3 Units Notes
Parameter Address Access Time ADV# Access Time Page Access Time Address Hold from ADV# HIGH Address Setup to ADV# HIGH LB#/UB# Access Time LB#/UB# Disable to DQ High-Z Output LB#/UB# Enable to Low-Z Output CE# HIGH between Subsequent Mixed-Mode Operations Maximum CE# Pulse Width CE# LOW to WAIT Valid Chip Select Access Time CE# LOW to ADV# HIGH Chip Disable to DQ and WAIT High-Z Output Chip Enable to Low-Z Output Output Enable to Valid Output Output Hold from Address Change Output Disable to DQ High-Z Output Output Enable to Low-Z Output Page Cycle Time READ Cycle Time ADV# Pulse Width LOW ADV# Pulse Width HIGH
Symbol tAA tAADV tAPA tAVH tAVS tBA tBHZ tBLZ tCBPH tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP tVPH
Min
Max 85 85 25
5 10
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. See "How Extended Timings Impact CellularRAMTM Operation" below. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 5. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
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Table 32.
Burst READ Cycle Timing Requirements
70ns/80 MHz 85ns/66 MHz Min Max 55 11 10 20 5 1 12.5 4 2 8 1.6 9 3 2 2 3 8 5 3 5 3 8 5 3 2 2 3 8 7.5 5 1 15 5 2 8 1.6 11 8 5 7.5 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 3 2 Notes
Parameter Burst to READ Access Time (Variable Latency) CLK to Output Delay Address Setup to ADV# HIGH Burst OE# LOW to Output Delay CE# HIGH between Subsequent Mixed-Mode Operations CE# LOW to WAIT Valid CLK Period CE# Setup Time to Active CLK Edge Hold Time from Active CLK Edge Chip Disable to DQ and WAIT High-Z Output CLK Rise or Fall Time CLK to WAIT Valid CLK to DQ High-Z Output CLK to Low-Z Output Output HOLD from CLK CLK HIGH or LOW Time Output Disable to DQ High-Z Output Output Enable to Low-Z Output Setup Time to Active CLK Edge
Symbol tABA tACLK tAVS tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKHZ tKLZ tKOH tKP tOHZ tOLZ tSP
Min
Max 35 9
10
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
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Table 33.
Asynchronous WRITE Cycle Timing Requirements
70ns/80 MHz 85ns/66 MHz Min 0 5 10 85 85 4 1 70 10 70 0 23 8 10 5 10 10 70 70 8 46 10 0 55 10 0 10 5 10 10 85 85 8 7.5 1 85 10 85 0 23 8 4 7.5 ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 3 3 1 1 Max Units ns ns Notes
Parameter Address and ADV# LOW Setup Time Address Hold from ADV# Going HIGH Address Setup to ADV# Going HIGH Address Valid to End of Write LB#/UB# Select to End of Write Maximum CE# Pulse Width CE# LOW to WAIT Valid Async Address-to-Burst Transition Time CE# Low to ADV# HIGH Chip Enable to End of Write Data Hold from Write Time Data WRITE Setup Time Chip Disable to WAIT High-Z Output Chip Enable to Low-Z Output End WRITE to Low-Z Output ADV# Pulse Width ADV# Pulse Width HIGH ADV# Setup to End of WRITE WRITE Cycle Time WRITE to DQ High-Z Output WRITE Pulse Width WRITE Pulse Width HIGH WRITE Recovery Time
Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCKA tCVS tCW tDH tDW tHZ tLZ tOW tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 0 5 10 70 70
Max
Notes: 1. See "How Extended Timings Impact CellularRAMTM Operation" below. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
Table 34.
Burst WRITE Cycle Timing Requirements
70ns/80 MHz 85ns/66 MHz Min 5 7.5 1 7.5 Max Units ns ns Notes
Parameter CE# HIGH between Subsequent Mixed-Mode Operations CE# LOW to WAIT Valid
Symbol tCBPH tCEW
Min 5 1
Max
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Table 34.
Burst WRITE Cycle Timing Requirements (Continued)
70ns/80 MHz 85ns/66 MHz Min 15 5 2 8 1.6 9 3 3 3 3 8 1.6 11 Max Units ns ns ns ns ns ns ns ns Notes
Parameter Clock Period CE# Setup to CLK Active Edge Hold Time from Active CLK Edge Chip Disable to WAIT High-Z Output CLK Rise or Fall Time Clock to WAIT Valid CLK HIGH or LOW Time Setup Time to Activate CLK Edge
Symbol tCLK tCSP tHD tHZ tKHKL tKHTL tKP tSP
Min 12.5 4 2
Max
Timing Diagrams
VCC, VCCQ = 1.7V
VCC (MIN) tPU Device ready for normal operation
Figure 39. Table 35.
Initialization Period
Initialization Timing Parameters
70ns/80 MHz 85ns/66 MHz Min Max 150 Units s Notes
Parameter Initialization Period (required before normal operations)
Symbol tPU
Min
Max 150
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t RC A[22:0] V IH V IL t AA V IH V IL t CBPH CE# V IH V IL t CO t BA LB#/UB# V IH V IL t OE OE# V IH V IL V IH V IL t OLZ t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z t OHZ t BHZ t HZ VALID ADDRESS
ADV#
WE#
DQ[15:0]
VALID OUTPUT t HZ High-Z
WAIT
Figure 40. Table 36.
Asynchronous READ
Asynchronous READ Timing Parameters
85ns/66 MHz Max 70 70 8 Min Max 85 85 8 10 5 Units ns ns ns ns ns
70ns/80 MHz Symbol tAA tBA tBHZ tBLZ tCBPH 10 5 Min
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Table 36.
Asynchronous READ Timing Parameters (Continued)
70ns/80 MHz 85ns/66 MHz Max 7.5 70 8 8 10 20 8 20 8 5 85 Min 1 Max 7.5 Units ns ns ns ns ns ns ns ns
Symbol tCEW tCO tHZ tLZ tOE tOHZ tOLZ tRC
Min 1
10
5 70
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A[22:0]
V IH V IL
VALID ADDRESS t AA t AVS t AVH
t VPH ADV# V IH V IL
t AADV t VP t CBPH t CVS t HZ
CE#
V IH V IL t CO t BA t BHZ
LB#/UB#
V IH V IL t OE t OHZ
OE#
V IH V IL V IH V IL t OLZ t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z
WE#
DQ[15:0]
VALID OUTPUT t HZ High-Z
WAIT
Figure 41. Table 37.
Asynchronous READ Using ADV#
Asynchronous READ Timing Parameters Using ADV#
70ns/80 MHz 85ns/66 MHz Max 70 70 Min Max 85 85 Units ns ns
Symbol tAA tAADV
Min
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Table 37.
Asynchronous READ Timing Parameters Using ADV# (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 10 5 10 70 8 10 5 1 7.5 70 10 8 10 20 8 5 10 10 5 10 10 10 20 8 10 8 10 5 1 7.5 85 85 8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tCVS tAVH tAVS tBA tBHZ tBLZ tCBPH tCEW tCO tCVS tHZ tLZ tOE tOHZ tOLZ tVP tVPH
Min 10 5 10
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t RC A[22:0] V IH V IL V IH V IL VALID ADDRESS t AA V IH V IL t CEM t CBPH CE# V IH V IL t BA LB#/UB# V IH V IL t OE OE# V IH V IL V IH V IL t BLZ t LZ V OH V OL t CEW V IH V IL Legend: Don't Care Undefined High-Z High-Z t OLZ t APA t OH t OHZ t BHZ t CO t CBPH t HZ VALID ADDRESS
A[3:0]
VALID ADDRESS t PC
VALID ADDRESS
VALID ADDRESS
ADV#
WE#
DQ[15:0]
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT t HZ High-Z
WAIT
Figure 42. Table 38.
Page Mode READ
Asynchronous READ Timing Parameters--Page Mode Operation
70ns/80 MHz 85ns/66 MHz Max 70 20 70 8 Min Max 85 25 85 8 Units ns ns ns ns
Symbol tAA tAPA tBA tBHZ
Min
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Table 38.
Asynchronous READ Timing Parameters--Page Mode Operation (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 10 5 4 1 7.5 70 8 10 20 5 8 5 20 70 5 25 85 5 8 10 20 1 4 7.5 85 8 Max Units ns ns s ns ns ns ns ns ns ns ns ns ns
Symbol tBLZ tCBPH tCEM tCEW tCO tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC
Min 10 5
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t CLK V IH V IL t KHKL t SP A[22:0] V IH V IL t HD
t KP
t KP
CLK
VALID ADDRESS t SP t HD
ADV#
V IH V IL t HD t CSP t ABA t HZ
CE#
V IH V IL t BOE t OHZ
OE#
V IH V IL
t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL High-Z
t HD
t OLZ
t HD
t KHTL High-Z
WAIT
t ACLK DQ[15:0] V OH V OL High-Z
t KOH VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 43. Table 39.
Single-Access Burst READ Operation--Variable Latency
Burst READ Timing Parameters--Single Access, Variable Latency
70ns/80 MHz 85ns/66 MHz Max 35 9 Min Max 55 11 Units ns ns
Symbol tABA tACLK
Min
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Table 39.
Burst READ Timing Parameters--Single Access, Variable Latency (Continued)
70ns/80 MHz 85ns/66 MHz Max 20 1 12.5 4 2 8 1.6 9 2 3 8 5 3 5 3 2 3 8 7.5 1 15 5 2 8 1.6 11 Min Max 20 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tBOE tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP
Min
140
CellularRAM Type 2
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t KHKL CLK V IH V IL t SP A[22:0] V IH V IL t HD
t CLK
t KP
t KP
Valid Address t SP t HD
ADV#
V IH V IL t CSP t ABA t HD t CBPH
CE#
V IH V IL t HZ
OE#
V IH V IL t SP t HD t OLZ
t BOE
t OHZ
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V OH V OL t KOH t ACLK High-Z t KHTL High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 44.
Four-word Burst READ Operation--Variable Latency
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Table 40.
Burst READ Timing Parameters--4-word Burst
85ns/66 MHz Max 35 9 20 Min Max 55 11 20 5 7.5 1 15 5 2 8 1.6 9 8 1.6 11 2 3 8 8 5 3 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tABA tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP 5 3 2 3 5 1 12.5 4 2 Min
142
CellularRAM Type 2
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Information
t CLK V IH V IL t SP A[22:0] V IH V IL t HD
CLK
Valid Address t SP t HD
ADV#
V IH V IL t CSP t HD t CBPH
CE#
V IH V IL t HZ
OE#
V IH V IL t SP t HD t OLZ
t BOE
t OHZ
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V OH V OL t KOH t ACLK t KHTL t KHTL t KHTL High-Z t KHTL High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
VALID OUTPUT
READ Burst Identified (WE# = HIGH)
Legend:
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 45.
Four-word Burst READ Operation (with LB#/UB#)
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Table 41.
Burst READ Timing Parameters--4-word Burst with LB#/UB#
70ns/80 MHz 85ns/66 MHz Max 9 20 5 1 7.5 5 1 15 5 2 8 9 3 2 2 8 5 3 5 3 8 5 3 2 2 8 8 11 8 5 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHTL tKHZ tKLZ tKOH tOHZ tOLZ tSP
Min
12.5 4 2
144
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t CLK V IH V IL t SP A[22:0] V IH V IL t HD Valid Address
CLK
Valid Address t HD t SP
ADV#
V IH V IL t CBPH t CSP t HZ
CE#
V IH V IL t OHZ t OHZ
OE#
V IH V IL t SP t HD
(Note 2)
WE#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CEW V IH V IL t KOH t ACLK t OLZ t BOE High-Z t OLZ t BOE High-Z
WAIT
DQ[15:0]
V OH V OL
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
Legend:
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
Figure 46. Table 42.
READ Burst Suspend
Burst READ Timing Parameters--Burst Suspend
85ns/66 MHz Max 9 20 Min Max 11 20 5 15 5 2 8 8 2 8 8 5 Units ns ns ns ns ns ns ns ns ns ns
70ns/80 MHz Symbol tACLK tBOE tCBPH tCLK tCSP tHD tHZ tKOH tOHZ tOLZ 5 2 5 12.5 4 2 Min
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Table 42.
Burst READ Timing Parameters--Burst Suspend (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 3 Max Units ns
Symbol tSP
Min 3
CLK
V IH V IL t CLK
A[22:0]
V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL t KHTL t KHTL t OHZ
ADV#
LB#/UB#
CE#
OE#
WE#
WAIT
V OH V OL
(Note 2)
t ACLK DQ[15:0] V OH V OL VALID OUTPUT VALID OUTPUT VALID OUTPUT
t KOH VALID OUTPUT
Legend:
Don't Care
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 47.
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Table 43. Burst READ Timing Parameters--BCR[8] = 0
85ns/66 MHz Max 9 12.5 9 2 2 15 11 Min Max 11 Units ns ns ns ns
70ns/80 MHz Symbol tACLK tCLK tKHTL tKOH Min
146
CellularRAM Type 2
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t AA A[22:0] V IH V IL VALID ADDRESS t AW t AS V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL High-Z VALID INPUT t DH t WP t WR
ADV#
OE#
t LZ
t WHZ
DQ[15:0] V OH OUT V OL t CEW V IH V IL High-Z
t HZ High-Z
WAIT
Legend:
Don't Care
Figure 48. Table 44.
CE#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters--CE#-Controlled
70ns/80 MHz 85ns/66 MHz Max Min 0 85 85 4 4 Max Units ns ns ns s
Symbol tAS tAW tBW tCEM
Min 0 70 70
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Table 44.
Asynchronous WRITE Timing Parameters--CE#-Controlled (Continued)
70ns/80 MHz 85ns/66 MHz Max 7.5 Min 1 85 0 23 8 10 70 8 46 10 0 55 10 0 10 85 8 8 Max 7.5 Units ns ns ns ns ns ns ns ns ns ns ns
Symbol tCEW tCW tDH tDW tHZ tLZ tWC tWHZ tWP tWPH tWR
Min 1 70 0 23
148
CellularRAM Type 2
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t WC A[22:0] V IH V IL VALID ADDRESS t AW t AS V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL High-Z VALID INPUT t DH t WP t WR
ADV#
OE#
t LZ
t WHZ
DQ[15:0] V OH OUT V OL t CEW V IH V IL High-Z
t HZ High-Z
WAIT
Legend:
Don't Care
Figure 49. Table 45.
LB#/UB#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled
70ns/80 MHz 85ns/66 MHz Max Min 0 85 85 Max Units ns ns ns
Symbol tAS tAW tBW
Min 0 70 70
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Table 45.
Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled (Continued)
70ns/80 MHz 85ns/66 MHz Max 4 1 70 0 23 8 10 70 8 46 10 0 55 10 0 10 85 8 7.5 1 85 0 23 8 Min Max 4 7.5 Units s ns ns ns ns ns ns ns ns ns ns ns
Symbol tCEM tCEW tCW tDH tDW tHZ tLZ tWC tWHZ tWP tWPH tWR
Min
150
CellularRAM Type 2
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t WC A[22:0] V IH V IL VALID ADDRESS t AW t WR V IH V IL t CEM t CW CE# V IH V IL t BW LB#/UB# V IH V IL V IH V IL t AS t WPH WE# V IH V IL t DW DQ[15:0] V IH IN V IL t LZ DQ[15:0] V OH OUT V OL t CEW V IH V IL Legend: High-Z t HZ High-Z High-Z t DH t WP
ADV#
OE#
VALID INPUT t WHZ t OW
WAIT
Don't Care
Figure 50. Table 46.
WE#-Controlled Asynchronous WRITE
Asynchronous WRITE Timing Parameters--WE#-Controlled
70ns/80 MHz 85ns/66 MHz Max Min 0 Max Units ns
Symbol tAS
Min 0
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Table 46.
Asynchronous WRITE Timing Parameters--WE#-Controlled (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 85 85 4 1 70 0 23 8 10 5 70 8 46 10 0 55 10 0 10 5 85 8 7.5 1 85 0 23 8 4 7.5 Max Units ns ns s ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tOW tWC tWHZ tWP tWPH tWR
Min 70 70
152
CellularRAM Type 2
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A[22:0]
V IH V IL
VALID ADDRESS t AVS t AVH t VS t VPH t AS t VP
ADV#
V IH V IL t AS t AW t CEM t CW
CE#
V IH V IL t BW
LB#/UB#
V IH V IL V IH V IL
OE#
t WP WE# V IH V IL t DW DQ[15:0] V IH IN V IL t LZ DQ[15:0] V OH OUT V OL t CEW V IH V IL Legend: High-Z t HZ High-Z
t WPH
t DH
VALID INPUT t WHZ t OW
WAIT
High-Z
Don't Care
Figure 51.
Asynchronous WRITE Using ADV#
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Table 47.
Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz 85ns/66 MHz Max Min 0 5 10 85 85 4 4 1 85 0 23 8 8 10 5 0 10 10 85 8 8 55 10 7.5 Max Units ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCW tDH tDW tHZ tLZ tOW tAS tVP tVPH tVS tWHZ tWP tWPH
Min 0 5 10 70 70
1 70 0 23
7.5
10 5 0 10 10 70
46 10
154
CellularRAM Type 2
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t KHKL t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD t KP t KP
Valid Address t SP t HD
ADV#
V IH V IL t SP t HD
LB#/UB#
V IH V IL t CSP t HD t CBPH
CE#
V IH V IL V IH V IL V IH V IL t CEW V IH V IL t SP t HD D[2] D[3] D[0] High-Z (Note 2) t KHTL t OHZ t HZ High-Z t SP t HD
OE#
WE#
WAIT
DQ[15:0]
V OH V OL
D[1]
READ Burst Identified (WE# = LOW)
Legend:
Don't Care
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled.
Figure 52.
Burst WRITE Operation
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Table 48.
70ns/80 MHz Symbol tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKP tSP 3 3 Min 5 1 12.5 4 2
Burst WRITE Timing Parameters
85ns/66 MHz Max Min 5 7.5 1 15 5 2 8 1.6 9 3 3 8 1.6 11 7.5 Max Units ns ns ns ns ns ns ns ns ns ns
156
CellularRAM Type 2
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Information
CLK
V IH V IL t CLK
A[22:0]
V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL t SP t HD
Valid Input Valid Input D[n+3] D[n+2]
ADV#
LB#/UB#
CE#
WE#
t OHZ
OE#
t KHTL
(Note 2)
t KHTL
WAIT
DQ[15:0]
V OH V OL
Valid Input Valid Input D[n] D[n+1]
END OF ROW
Legend:
Don't Care
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 53.
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Table 49. Burst WRITE Timing Parameters--BCR[8] = 0
85ns/66 MHz Max Min 15 2 8 3 11 3 Max Units ns ns ns ns
70ns/80 MHz Symbol tCLK tHD tKHTL tSP Min 12.5 2
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t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD t SP t HD
Valid Address
Valid Address t SP
t SP ADV# V IH V IL
t HD
t HD
t SP LB#/UB# V IH V IL t CSP CE# V IH V IL
t HD
t HD
t CBPH
(Note 2) V IH V IL t SP WE# V IH V IL V OH V OL t SP DQ[15:0] V IH V IL High-Z t HD D[1] D[2] D[3] High-Z t HD
t CSP
t OHZ
OE#
t SP
t HD
t BOE
WAIT
High-Z
t ACLK V OH V OL High-Z
t KOH Valid Output Valid Output Valid Output Valid Output
D[0]
Legend:
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE operations. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 54. Table 50.
Burst WRITE Followed by Burst READ
WRITE Timing Parameters--Burst WRITE Followed by Burst READ
70ns/80 MHz 85ns/66 MHz Max Min 5 20 20 15 5 2 3 20 20 Max Units ns ns ns ns ns
Symbol tCBPH tCLK tCSP tHD tSP
Min 5 12.5 4 2 3
Table 51.
READ Timing Parameters--Burst WRITE Followed by Burst READ
70ns/80 MHz 85ns/66 MHz Max Min 11 20 12.5 15 Max ns 20 ns ns Units
Symbol tACLK tBOE tCLK
Min 9
158
CellularRAM Type 2
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Table 51.
READ Timing Parameters--Burst WRITE Followed by Burst READ (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 5 2 2 8 3 3 8 Max Units ns ns ns ns ns
Symbol tCSP tHD tKOH tOHZ tSP
Min 4 2 2
t CLK CLK V IH V IL t WC A[22:0] V IH V IL Valid Address t AVS t VPH ADV# V IH V IL t VP t CVS LB#/UB# V IH V IL t CW CE# V IH V IL (Note 2) OE# V IH V IL t WC t AS V IH V IL t CEW V OH V OL t WHZ DQ[15:0] V IH V IL High-Z DATA t DH DATA t DW V OH V OL High-Z t ACLK Valid Output t KOH Valid Output Valid Output Valid Output t BOE High-Z t WP t WPH t OHZ t CBPH t CSP t VS t BW t SP t HD t AVH t WC Valid Address t AW t WR t SP t HD t CKA t SP t HD
Valid Address
t SP
t HD
WE#
WAIT
Legend:
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 55.
Asynchronous WRITE Followed by Burst READ
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Table 52.
WRITE Timing Parameters--Asynchronous WRITE Followed by Burst READ
70ns/80 MHz 85ns/66 MHz Max Min 5 0 10 85 85 85 10 85 0 23 10 10 85 85 8 46 10 0 55 10 0 8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tAVH tAS tAVS tAW tBW tCKA tCVS tCW tDH tDW tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 5 0 10 70 70 70 10 70 0 20 10 10 70 70
Table 53.
READ Timing Parameters--Asynchronous WRITE Followed by Burst READ
70ns/80 MHz 85ns/66 MHz Max 9 20 5 1 12.5 4 2 2 8 3 3 7.5 5 1 15 5 2 2 8 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns
Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tKOH tOHZ tSP
Min
160
CellularRAM Type 2
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Information
t CLK CLK V IH V IL t WC A[22:0] V IH V IL Valid Address t WC Valid Address t AW t WR t SP ADV# V IH V IL t BW LB#/UB# V IH V IL t CW CE# V IH V IL (Note 2) OE# V IH V IL t WC t WP t WPH WE# V IH V IL t CEW WAIT V OH V OL t WHZ DQ[15:0] V IH V IL High-Z DATA DATA t DW V OH V OL High-Z t ACLK t KOH Valid Output Valid Output Valid Output Valid Output t BOE High-Z t SP t HD t OHZ t CSP t CSP t SP t HD t HD t CKA t SP t HD
Valid Address
t DH Legend:
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 56.
Asynchronous WRITE (ADV# LOW) Followed By Burst READ Asynchronous WRITE Timing Parameters--ADV# LOW
70ns/80 MHz 85ns/66 MHz Max Min 85 85 85 85 0 23 85 8 8 Max Units ns ns ns ns ns ns ns ns
Table 54.
Symbol tAW tBW tCKA tCW tDH tDW tWC tWHZ
Min 70 70 70 70 0 23 70
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Table 54.
Asynchronous WRITE Timing Parameters--ADV# LOW (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 55 10 0 Max Units ns ns ns
Symbol tWP tWPH tWR
Min 46 10 0
Table 55.
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tKOH tOHZ tSP 3 5 1 12.5 4 2 2 Min
Burst READ Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 2 8 3 8 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns
162
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004
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Information
t CLK CLK V IH V IL t SP t HD A[22:0] V IH V IL Valid Address t SP t HD ADV# V IH V IL t CBPH t HD t CSP CE# V IH V IL t BOE OE# V IH V IL t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL t DW t ACLK DQ[15:0] V IH V IL High-Z t KOH Valid Output Valid Input t DH High-Z t KHTL t CEW High-Z t HZ t HD t BW t HD t OLZ t AS t WP t WPH t HZ (Note 2) t OHZ t CEM t CW t WC Valid Address t AW t WR
WAIT
Legend: READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 57.
Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
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Table 56.
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ 2 3 5 1 12.5 4 2 Min
Burst READ Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 8 1.6 9 2 3 8 8 8 1.6 11 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 57.
Asynchronous WRITE Timing Parameters--WE# Controlled
70ns/80 MHz 85ns/66 MHz Max Min Max 0 85 85 4 4 85 0 23 8 8 85 55 10 0 Units ns ns ns s ns ns ns ns ns ns ns ns
Symbol
tAS
Min 0 70 70
tAW tBW tCEM tCW tDH tDW tHZ tWC tWP tWPH tWR
70 0 23
70 46 10 0
164
CellularRAM Type 2
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Information
t CLK CLK V IH V IL t SP A[22:0] V IH V IL t HD Valid Address t AVS t SP t HD ADV# V IH V IL t AW t CBPH t HD t CSP CE# V IH V IL t BOE OE# V IH V IL t SP WE# V IH V IL t SP LB#/UB# V IH V IL t CEW V OH V OL t DW t ACLK DQ[15:0] V OH V OL High-Z t KOH Valid Output Valid Input t DH High-Z t KHTL t CEW High-Z t HZ t HD t BW t HD t OLZ t AS t WP t WPH t HZ (Note 2) t OHZ t AS t CEM t CW t VPH t VP t AVH t VS
Valid Address
WAIT
Legend: READ Burst Identified (WE# = HIGH)
Don't Care
Undefined
Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 58.
Burst READ Followed by Asynchronous WRITE Using ADV#
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Information
Table 58.
70ns/80 MHz Symbol tACLK tBOE tCBPH tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ 2 3 5 1 12.5 4 2 Min
Burst READ Timing Parameters
85ns/66 MHz Max 9 20 5 7.5 1 15 5 2 8 1.6 9 2 3 8 8 8 1.6 11 7.5 Min Max 11 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 59.
Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz 85ns/66 MHz Max Min 0 5 10 85 85 4 4 1 85 0 23 8 8 10 10 85 55 10 7.5 Max Units ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns
Symbol tAS tAVH tAVS tAW tBW tCEM tCEW tCW tDH tDW tHZ tVP tVPH tVS tWP tWPH
Min 0 5 10 70 70
1 70 0 23
7.5
10 10 70 46 10
166
CellularRAM Type 2
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Information
Table 59.
Asynchronous WRITE Timing Parameters Using ADV# (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 0 Max Units ns
Symbol tWR
Min 0
A[22:0]
V IH V IL
Valid Address
Valid Address t AW t WR t AA
Valid Address
ADV#
V IH V IL t BW t BLZ t BHZ
LB#/UB#
V IH V IL t CW t CBPH t CEM t HZ
CE#
V IH V IL (Note) t LZ t OE t OHZ
OE#
V IH V IL t WC t AS V IH V IL t HZ V OH V OL t WHZ V IH V IL High-Z DATA t DH DATA t DW High-Z V OH V OL Legend: t OLZ t HZ t WP t WPH
WE#
WAIT
DQ[15:0]
Valid Output
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 59.
Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW Table 60. WRITE Timing Parameters--ADV# LOW
85ns/66 MHz Max Min 0 85 85 85 Max Units ns ns ns ns
70ns/80 MHz Symbol tAS tAW tBW tCW Min 0 70 70 70
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Table 60.
WRITE Timing Parameters--ADV# LOW (Continued)
70ns/80 MHz 85ns/66 MHz Max Min 0 23 8 8 85 8 8 55 10 0 Max Units ns ns ns ns ns ns ns ns
Symbol tDH tDW tHZ tWC tWHZ tWP tWPH tWR
Min 0 23
70
46 10 0
Table 61.
READ Timing Parameters--ADV# LOW
85ns/66 MHz Max 70 8 Min Max 85 8 10 5 4 8 4 8 10 20 8 20 8 5 Units ns ns ns ns s ns ns ns ns ns
70ns/80 MHz Symbol tAA tBHZ tBLZ tCBPH tCEM tHZ tLZ tOE tOHZ tOLZ 5 10 10 5 Min
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A[22:0]
V IH V IL
Valid Address t AVS t AVH
Valid Address t AW t WR
Valid Address t AA
t VPH t VP ADV# V IH V IL t CVS LB#/UB# V IH V IL t CW CE# V IH V IL
t VS
t BW
t BLZ
t BHZ
t CBPH
t CEM
t HZ
t AS V IH V IL t WC t AS V IH V IL V OH V OL t WHZ V IH V IL High-Z DATA t DH DATA t DW t WP t WPH
(Note)
t LZ
t OHZ
OE#
t OLZ
WE#
WAIT
t OE V OH V OL Legend: High-Z
DQ[15:0]
Valid Output
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See "How Extended Timings Impact CellularRAMTM Operation" for restrictions on the maximum CE# LOW time (tCEM).
Figure 60. Table 62.
Asynchronous WRITE Followed by Asynchronous READ
WRITE Timing Parameters--Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz 85ns/66 MHz Max Min 0 5 10 85 85 10 85 0 23 Max Units ns ns ns ns ns ns ns ns ns
Symbol tAS tAVH tAVS tAW tBW tCVS tCW tDH tDW
Min 0 5 10 70 70 10 70 0 23
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Table 62.
WRITE Timing Parameters--Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz 85ns/66 MHz Max Min 10 10 85 85 8 46 10 0 55 10 0 8 Max Units ns ns ns ns ns ns ns ns
Symbol tVP tVPH tVS tWC tWHZ tWP tWPH tWR
Min 10 10 70 70
Table 63.
READ Timing Parameters--Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz 85ns/66 MHz Max 70 8 10 5 4 8 10 20 8 5 5 10 20 8 10 5 4 8 Min Max 85 8 Units ns ns ns ns s ns ns ns ns ns
Symbol tAA tBHZ tBLZ tCBPH tCEM tHZ tLZ tOE tOHZ tOLZ
Min
How Extended Timings Impact CellularRAMTM Operation
Introduction
This section describes CellularRAMTM timing requirements in systems that perform extended operations. CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry imposes constraints on timings in systems that take longer than 4s to complete an operation. WRITE operations are affected if the device is configured for asynchronous operation. Both READ and WRITE operations are affected if the device is configured for page or burst-mode operation.
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Asynchronous WRITE Operation
The timing parameters provided in Figure 33 require that all WRITE operations must be completed within 4s. After completing a WRITE operation, the device must either enter standby (by transitioning CE# HIGH), or else perform a second operation (READ or WRITE) using a new address. Figure 61 and Figure 62 demonstrate these constraints as they apply during an asynchronous (page-modedisabled) operation. Either the CE# active period (tCEM in Figure 61) or the address valid period (tTM in Figure 62) must be less than 4s during any WRITE operation, otherwise, the extended WRITE timings must be used.
tCEM < 4 s CE# ADDRESS
Figure 61.
Extended Timing for tCEM
CE# tTM < 4s ADDRESS
Figure 62. Table 64.
Page Mode Asynchronous Page Mode Disabled Asynchronous Page Mode Enabled Burst
Extended Timing for tTM
Extended Cycle Impact on READ and WRITE Cycles
Read Cycle No impact. Write Cycle Must use extended WRITE timing. (See Figure 62) Must use extended WRITE timing. (See Figure 63)
Timing Constraint tCEM and tTM > 4s (See Figure 61 and Figure 62.) tCEM > 4s (See Figure 61.) tCEM > 4s (See Figure 61.)
All following intrapage READ access times are tAA (not tAPA).
Burst must cross a row boundary within 4s.
Extended WRITE Timing-- Asynchronous WRITE Operation
Modified timings are required during extended WRITE operations (see Figure 63). An extended WRITE operation requires that both the write pulse width (tWP) and the data valid period (tDW) be lengthened to at least the minimum WRITE cycle time (tWC [MIN]). These increased timings ensure that time is available for both a refresh operation and a successful completion of the WRITE operation.
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t CEM or t TM > 4s ADDRESS
CE#
LB#/UB# t WP > t WC (MIN) WE#
t DW > t WC (MIN) DATA-IN
Figure 63.
Extended WRITE Operation
Page Mode READ Operation
When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. If CE# is LOW longer than the tCEM maximum time of 4s during a READ operation, the system must allow tAA (not tAPA, as would otherwise be expected) for all subsequent intrapage accesses until CE# goes HIGH.
Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 4s window. One of two conditions will enable the device to schedule a refresh within 4s. The first condition is when all burst operations complete within 4s. A burst completes when the CE# signal is registered HIGH on a rising clock edge. The second condition that allows a refresh is when a burst access crosses a row boundary. The row-boundary crossing causes WAIT to be asserted while the next row is accessed and enables the scheduling of refresh.
Summary
CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings on asynchronous WRITE operations require that tWP and tDW be lengthened. Slow bus timings during asynchronous page READ operations cause the next intrapage READ data to be delayed to tAA. Burst mode timings must allow the device to perform a refresh within any 4s period. A burst operation must either complete (CE# registered HIGH) or cross a row boundary within 4s to ensure successful refresh scheduling. These timing requirements are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus.
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CellularRAM-2A
64 Megabit Asynchronous CellularRAM
Features
Asynchronous and Page Mode interface Random Access Time: 70 ns Page Mode Read Access
-- Sixteen-word page size -- Interpage read access: 70 ns -- Intrapage read access: 20 ns
VCC, VCCQ Voltages
-- 1.70 V to 1.95 V VCC -- 1.70 V to 2.25 V VCCQ
Low Power Consumption
-- Asynchronous READ < 25 mA -- Intrapage READ < 15 mA -- Standby: 100 A -- Deep power-down < 10 A
Low-Power Features
-- Temperature Compensated Refresh (TCR) -- Partial Array Refresh (PAR) -- Deep Power-Down (DPD) Mode
General Description
CellularRAMTM products are high-speed, CMOS dynamic random access memories that have been developed for low-power portable applications. The 64Mb device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. A user-accessible configuration register (CR) has been included to define device operation. The CR defines how the CellularRAM device performs on-chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. To operate smoothly on an asynchronous memory bus, CellularRAM products have incorporated a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Special attention has been focused on current consumption during self refresh. CellularRAM products include three system-accessible mechanisms used to minimize refresh current. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the case temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Setting the sleep enable pin ZZ# to LOW enables one of two low-power modes: partial array refresh (PAR); or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh oper-
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ation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the CR.
A[21:0]
Address Decode Logic
4,096K x 16 DRAM Memory Array
Input/ Output MUX and Buffers
DQ[7:0]
Configuration Register (CR)
DQ[15:8]
CE# WE# OE# LB# UB# ZZ# Control Logic
Note: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams for detailed information.
Figure 64.
Functional Block Diagram Pin Descriptions
Description
Table 65.
Symbol A[21:0] ZZ# CE# OE# WE# LB# UB# DQ[15:0] VCC VCCQ VSS Type Input Input Input Input Input Input Input Input/ Output Supply Supply Supply
Address Inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the configuration register. Sleep Enable: When ZZ# is LOW, the configuration register can be loaded or the device can enter one of two low-power modes (DPD or PAR). Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Enables WRITE operations when LOW. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. Device Power Supply: (1.7 V-1.95 V) Power supply for device core operation. I/O Power Supply: (1.8 V) Power supply for input/output buffers. VSS must be connected to ground.
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Table 65.
Symbol VSSQ Type Supply
Pin Descriptions (Continued)
Description
VSSQ must be connected to ground.
Table 66.
Mode Standby Read Write Active PAR DPD Load Configuration Register Power Standby
Bus Operations--Asynchronous Mode
CE# H L L L H H L WE# X H L H X X L OE# X L X H X X X LB#/UB# X L L L X X X ZZ# H H H H L L L DQ[15:0] (Note 1) High-Z Data-Out Data-In High-Z High-Z High-Z High-Z Notes 2, 5 1, 4 1, 3, 4 4, 5 6 6
Active > Standby Active > Standby Standby Partial Array Refresh Deep Power-down Active
Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are affected. 2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally isolated from any external influence. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os. 4. The device consumes active power in this mode whenever addresses are changed. 5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current. 6. DPD is enabled when configuration register bit CR[4] is "0"; otherwise, PAR is enabled.
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Functional Description
The 64Mb async/page CellularRAM device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The device contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. It includes the industry-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor that is used to launch the power-up initialization process. Initialization will load the CR with its default settings. VCC and VCCQ must be applied simultaneously, and when they reach a stable level above 1.70 V, the device requires 150 s to complete its self initialization process (see Figure 2). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. At power-up, the CR is set to 0070h.
VCC VCCQ
VCC = 1.7 V
tPU > 150 s Device Initialization
Device ready for normal operation
Figure 65.
Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate the industry-standard, asynchronous interface found on other low-power SRAM or Pseudo SRAM offerings. This bus interface supports asynchronous READ and WRITE operations as well as the bandwidthenhancing page mode READ operation. The specific interface that is supported is defined by the value loaded into the CR.
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry standard SRAM control interface (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 66) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 67) occur when CE#, WE#, and LB#/ UB# are driven LOW. During WRITE operations, the level of OE# is a "Don't Care"; WE# will override OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first).
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CE#
OE# WE# ADDRESS Address Valid
DATA
Data Valid
LB#/UB#
tRC = READ Cycle Time Don't Care
Figure 66.
READ Operation
CE#
OE#
WE#
ADDRESS
Address Valid
DATA
Data Valid
LB#/UB#
tWC = WRITE Cycle Time Don't Care
Figure 67.
WRITE Operation
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 68 shows the timing diagram for a page mode access.
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Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality.
CE#
OE# WE# ADDRESS ADD[0] ADD[1] ADD[2] ADD[3]
tAA DATA
tAPA D[0]
tAPA D[1]
tAPA D[2] D[3]
LB#/UB#
Don't Care
Figure 68.
Page Mode READ Operation
LB# / UB# Operation
The lower byte (LB#) enable and upper byte (UB#) enable signals allow for bytewide data transfers. During READ operations, enabled bytes are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, the device remains in an active mode as long as CE# remains LOW.
Low Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH and there are no transactions in progress. The device will enter standby operation during READ and WRITE operations where the address and control inputs remain static for an extended period of time. This "active" standby mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires more
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frequent refresh operations to maintain data integrity as temperatures increase. More frequent refresh is required due to the increased leakage of the DRAM's capacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds: +15C, +45C, +70C, and +85C. The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. Data stored in addresses not receiving refresh will become corrupted. The mapping of these partitions can start at either the beginning or the end of the address map (Tables 5 and 6). READ and WRITE operations are ignored during PAR operation. The device can only enter PAR mode if the SLEEP bit in the configuration register has been set HIGH (CR[4] = 1). PAR is initiated by bring the ZZ# pin to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause an exit from PAR and the entire array will be immediately available for READ and WRITE operations.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is entered. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. READ and WRITE operations are ignored during DPD operation. The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is initiated by bringing the ZZ# pin to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150s initialization process. During this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1).
Configuration Register Operation
The configuration register (CR) defines how the CellularRAM device performs its transparent self refresh. This register is automatically loaded with default settings during power-up and can be updated anytime while the device is operating in a standby state. The CR is loaded using a WRITE operation immediately after ZZ# makes a HIGHto-LOW transition (Figure 69). The values placed on addresses A[21:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. Al-
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tering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the configuration register. Table 67 describes the control bits used in the CR. At power up, the CR is set to 0070h.
ADDRESS
ADDRESS VALID
CE# WE# ZZ#
t < 500ns
Figure 69.
Load Configuration Register Operation
Partial Array Refresh (CR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the system to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 68 on page 181).
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. DPD operation disables all refresh-related activity. This mode will be used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operation can resume.
Temperature Compensated Refresh (CR[6:5]) Default = +85C Operation
The TCR bits allow for adequate refresh at four different temperature thresholds: +15C, +45C, +70C, and +85C. The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page mode is disabled.
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Table 67.
A[21:8] A7
Configuration Register Bit Mapping
A6 A5 A4 A3 A2 A1 A0 Address Bus
21-8
7
6
5
4
3
2
1
0
RESERVED
PAGE
TCR
SLEEP
RESERVED
PAR
Configuration Register
All must be set to "0"
Must be set to "0"
CR[2] CR[1] CR[0]
PAR Refresh Coverage
CR[7]
Page Mode Enable/Disable
0 0 0 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Full array (default) Bottom 3/4 array Bottom 1/2 array Bottom 1/4 array None of array Top 3/4 array Top 1/2 array Top 1/4 array
0 1
Page Mode Disabled (default) Page Mode Enabled
CR[6] CR[5]
Maximum Case Temp.
1 1 1
1 0 0 1
1 0 1 0
+85 +70 +45 +15
C (default) C C C
CR[4]
Sleep Mode
0 1
DPD Enabled PAR Enabled (default)
Table 68.
CR[2] 0 0 0 0 1 1 1 1 CR[1] 0 0 1 1 0 0 1 1 CR[0] 0 1 0 1 0 1 0 1
64Mb Address Patterns for PAR (CR[4] = 1)
Active Section Full die Address Space 000000h-3FFFFFh 000000h-2FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 0 100000h-3FFFFFh 200000h-3FFFFFh 300000h-3FFFFFh Size 4 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 0 Meg x 16 3 Meg x 16 2 Meg x 16 1 Meg x 16 Density 64Mb 48Mb 32Mb 16Mb 0Mb 48Mb 32Mb 16Mb
Three-quarters of die One-half of die One-quarter of die None of die Three-quarters of die One-half of die One-quarter of die
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Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ Relative to VSS . . . -0.50 V to (4.0 V or VCCQ + 0.3 V, whichever is less) Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . -0.20 V to +2.45 V Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . -0.20 V to +4.0 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Soldering Temperature and Time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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DC Characteristics
Wireless Temperature (-25C TC +85C) Industrial Temperature (-40C < TC < +85C)
Table 69.
Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read Operating Current Write Operating Current MAX Standby Current
Electrical Characteristics and Operating Conditions
Conditions Symbol VCC 1.8 V VCCQ VIH VIL IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled VIN = VCCQ or 0V Chip Enabled, IOUT = 0 VIN = VCCQ or 0V Chip Enabled VIN = VCCQ or 0V Chip Disabled VOH VOL ILI ILO ICC1 ICC2 ISB Min 1.70 1.70 1.4 -0.20 0.80 VCCQ 0.20 VCCQ 1 1 25 25 100 Max 1.95 2.25 VCCQ + 0.2 0.4 Units V V V V V V A A mA mA A 2 1, 2 1, 2 2, 3 Notes
Notes: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, LB#, and UB#. In order to achieve low standby current, all inputs must be either VCCQ or VSS. 3. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C.
Table 70.
Description
Temperature Compensated Refresh Specifications and Conditions
Conditions Symbol Density Max Case Temperature +85C Typ Max 100 TBD TBD 50 A Units
Temperature Compensated Refresh Standby Current
VIN = VCCQ or 0V, Chip Disabled
ITCR
64 Mb
+70C +45C +15C
Notes: 1. ITCR (MAX) values measured with FULL ARRAY refresh. 2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, LB#, and UB#. In order to achieve low standby current, all inputs must be either VCCQ or VSS.
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Table 71.
Description
Partial Array Refresh Specifications and Conditions
Conditions Symbol Density Array Partition Full Typ Max 100 TBD TBD TBD 50 A Units
Partially Array Refresh Current
VIN = VCCQ or 0V, ZZ# = Low CR[4] = 1
3/4 IPAR 64 Mb 1/2 1/4 0
Note:IPAR (MAX) values measured with TCR set to 85C.
Table 72.
Description Deep Power-down
Deep Power-Down Specifications
Conditions Symbol IZZ Typ Max 10 Units A
VIN = VCCQ or 0V; +25C; ZZ# = LOW CR[4] = 0
Table 73.
Description Input Capacitance Input/Output Capacitance (DQ)
Capacitance Specifications and Conditions
Conditions Symbol CIN CIO Min Max 6 6 Units pF pF Notes 1 1
TC = +25C; f = 1 MHz; VIN = 0V
Notes: 1. These parameters are verified in device characterization and are not 100% tested.
AC Characteristics
VCC Q Input VCCQ /2 Test Points VCCQ/2 Output VSS Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns.
Figure 70.
AC Input/Output Reference Waveform
VCCQ R1 DUT 30pF R2 Test Point
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 71. Table 74.
VCCQ 1.8 V
Output Load Circuit Output Load Circuit
R1/R2 2.7 K
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Table 75.
Parameter Address Access Time Page Access Time LB#/UB# Access Time
READ Cycle Timing Requirements
Symbol tAA tAPA tBA tBHZ tBLZ tCO tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC 5 0 5 20 70 8 0 10 20 0 10 70 8 Min Max 70 20 70 8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 2 1 2 1 Notes
LB#/UB# Disable to High-Z Output LB#/UB# Enable to Low-Z Output Chip Select Access Time Chip Disable to High-Z Output Chip Enable to Low-Z Output Output Enable to Valid Output Output Hold from Address Change Output Disable to High-Z Output Output Enable to Low-Z Output Page Cycle Time READ Cycle Time
Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
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Table 76.
Parameter Address Setup Time Address Valid to End of Write Byte Select to End of Write CE# HIGH Time During Write Maximum CE# Pulse Width Chip Enable to End of Write Data Hold from Write Time Data WRITE Setup Time Chip Enable to Low-Z Output End WRITE to Low-Z Output Write Cycle Time Write to High-Z Output Write Pulse Width Write Recovery Time
WRITE Cycle Timing Requirements
Symbol tAS tAW tBW tCEH tCEM tCW tDH tDW tLZ tOW tWC tWHZ tWP tWR 70 0 23 10 5 70 0 46 0 ns 8 Min 0 70 70 5 10 Max Units ns ns ns ns s ns ns ns ns ns ns ns 2 1 Notes
Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
Table 77.
Parameter Address Setup Time
Load Configuration Register Timing Requirements
Symbol tAS tAW tCDZZ tCW tWC tWP tWR tZZWE Min 0 70 5 70 70 40 0 10 Max Units ns ns ns ns ns ns ns ns Notes
Address Valid to End of Write Chip Deselect to ZZ# LOW Chip Enable to End of Write Write Cycle Time Write Pulse Width Write Recovery Time ZZ# LOW to WE# LOW
Table 78.
Parameter Chip Deselect to ZZ# LOW Deep Power-Down Recovery Minimum ZZ# Pulse Width
Deep Power Down Timing Requirements
Symbol tCDZZ tR tZZMIN Min 5 150 10 Max Units ns s s Notes
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Table 79.
Power-up Initialization Timing Parameters
Symbol tPU Min 150 Max Units s Notes
Parameter Initialization Period (required before normal operations)
VCC, VCCQ = 1.7V
VCC (MIN) tPU Device ready for normal operation
Figure 72.
Power-up Initialization Period
tWC
ADDRESS
OPCODE
tAW tWR
CE#
tCW
LB#/UB#
tAS tWP
WE# OE#
tCDZZ tZZWE
ZZ# DON'T CAR E
Figure 73. Table 80.
Symbol tAS tAW tCDZZ tCW
Load Configuration Register Timing
Load Configuration Register Timing Requirements
Min 0 70 5 70 ns Max Units Symbol tWC tWP tWR tZZWE Min 70 40 0 10 500 ns Max Units
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t CDZZ
t ZZ (MIN)
ZZ#
tR
CE#
Device ready for normal operatio n DON'T CAR E
Figure 74. Table 81.
Deep Power Down Entry/Exit TIming
Load Configuration Register Timing Requirements
Symbol tCDZZ tR tZZ(MIN) Min 5 150 10 Max Units ns s s
tRC
ADDRESS
ADDRESS VALID
tAA tHZ
CE#
tCO tBA tBHZ
LB#/UB#
tLZ tBLZ tOE tOHZ
OE#
tOLZ
DATA-OUT
High-Z
Data Valid
High-Z
DON'T CARE
UNDEFINED
Figure 75.
Single READ Operation (WE# = VIH)
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Table 82.
Symbol tAA tBA tBHZ tBLZ tCO tHZ 0 0 10 70 8 Min Max 70 70 8
READ Timing Parameters
Units Symbol tLZ tOE ns tOHZ tOLZ tRC 0 5 70 Min 10 20 8 ns Max Units
tRC
ADDRESS A[21:4] ADDRESS A[3:0]
ADDRESS VALID
tAA
tPC tHZ
CE#
tCO tBA tBHZ
LB#/UB#
tBLZ tLZ tOE tOHZ
OE#
tOLZ tAPA tOH
DATA-OUT
High-Z
Data Valid
Data Valid
Data Valid
Data Valid
High-Z
DON'T CARE
UNDEFINED
Figure 76. Table 83.
Symbol tAA tAPA tBA tBHZ tBLZ tCO tHZ 0 0 10 Min
Page Mode Read Operation (WE# = VIH) Page Mode READ Timing Parameters
Max 70 20 70 8 ns Units Symbol tLZ tOE tOH tOHZ tOLZ 70 8 tPC tRC 5 0 5 20 70 8 ns Min 10 20 Max Units
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tWC
ADDRESS
ADDRESS VALID
tAW tCEM tCW tWR
CE#
tBW
LB#/UB#
tAS tWP
WE# OE#
tDW tDH
DATA-IN
tWHZ
Data Valid
tOW
DATA-OUT
High-Z
DON'T CAR E
Figure 77. Table 84.
Symbol tAS tAW tBW tCEM tCW tDH 70 0 Min 0 70 70 10 Max
WRITE Cycle (WE# Control) Write Timing Parameters
Units Symbol tDW ns tOW tWC s ns tWHZ tWP tWR Min 23 5 70 0 46 0 8 ns Max Units
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tWC
ADDRESS
tAW tCW tWR tCEH
CE#
tAS tCEM tBW
LB#/UB#
tWP
WE# OE#
tDW tDH
DATA-IN
Data Valid
tLZ tWHZ
DATA-OUT
High-Z
DON'T CARE
Figure 78. Table 85.
Symbol tAS tAW tBW tCEH tCEM tCW tDH 70 0 Min 0 70 70 5
Write Timing Parameters (CE# Control) Write Timing Parameters (CE# Control)
Max Units Symbol tDW ns tLZ tWC tWHZ 10 s ns tWP tWR Min 23 10 70 0 46 0 8 ns Max Units
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tWC
ADDRESS
tAW tWR
CE#
tCEM
tAS
tBW
LB#/UB#
WE# OE#
tDW tDH
DATA-IN
tLZ
tWHZ
Data Valid
DATA-OUT
High-Z
DON'T CARE
Figure 79. Table 86.
Symbol tAS tAW tBW tCEM tDH 0 Min 0 70 70 10
WRITE Cycle (LB# / UB# Control)
Write Timing Parameters (LB# / UB# Control)
Max Units Symbol tDW ns tLZ tWC s ns tWHZ tWR Min 23 10 70 0 0 8 ns Max Units
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How Extended Timings Impact CellularRAMTM Operation
Introduction
CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry does impose constraints on timings in systems that take longer than 10s to complete WRITE operations. This section describes CellularRAM timing requirements in systems that perform extended operations.
Operation When Page Mode is Disabled
CellularRAM products require that all WRITE operations must be completed within 10s. After completing an operation, the device must either enter standby (by transitioning CE# HIGH), or else perform a second operation using a new address. Figures 80 and 81 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 80) or the address valid period (tTM in Figure 81) must be less than 10 s during any operation to accommodate orderly scheduling of refresh.
tCEM < 10 s CE# ADDRESS
Note:Timing constraints when page mode is enabled.
Figure 80.
Extended Timing for tCEM
CE# tTM < 10s ADDRESS
Note:Timing constraints when page mode is enabled.
Figure 81.
Extended Timing for tTM
Operation When Page Mode is Enabled
When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. CE# must return HIGH upon completion of all WRITE operations when page mode is enabled (Figure 82). The total time taken for a WRITE operation should not exceed 10 s to accommodate orderly scheduling of refresh.
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tCEM <10s
CE#
Note:Timing constraints when page mode is enabled.
Figure 82.
Extended Timing for tCEM (2)
Impact on Extended WRITE Operations
Modified timings are only required during extended WRITE operations (see Figure 83 below). An extended WRITE operation requires that both the write pulse width (tWP) and the data valid period (tDW) will need to be lengthened to at least the minimum WRITE cycle time (tWC[MIN]). These increased timings ensure that time is available for both a refresh operation and successful completion of the WRITE operation.
t CEM or t TM > 4s ADDRESS
CE#
LB#/UB# t WP > t WC (MIN) WE#
t DW > t WC (MIN) DATA-IN
Figure 83.
Extended WRITE Operation
Summary
CellularRAM products are designed to ensure that any possible bus timings do not cause corruption of array data due to lack of refresh. The on-chip refresh circuitry will only affect the required timings for WRITE operations (READs are unaffected) performed in a system with a slow memory interface. The impact for WRITE operations is that some of the timing parameters (tWP, tDW) are lengthened. The modified timings are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus.
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Revision Summary
Revision A0 (December 17, 2004)
Initial release.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of thirdparty rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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